Check out pms67.github.io/ if you would like to look through some of the PCB designs featured on this channel. I'll add more features/projects as time goes on! :)
That hint of tiredness in your voice when you said "vendors like to make their own package types" is something I feel in my bones. I've been digging into DrMOS parts (driver-integrated MOSFETs) and some of their pad layouts look like a box of pads that fell down the stairs. They frequently call them "QFN" but they're really LGA. The mechanical drawings are practically arcane heiroglyphs. I occasionally want to write "BE NOT AFRAID" next to them.
This video highlights an important consideration when choosing parts. The smaller QFN packages - especially with double rows, can introduce a STEEP price premium on the PCB manufacturing process. For example, needing to move down to sub-5mil tracks, and smaller vias, or even blind vias to access the pins. You can often find the exact same part in a slightly larger package that can save a lot of time and money per board, if you can spare a few extra mm in PCB size! There is obviously a point at which the smaller part becomes more viable when making large numbers of boards (otherwise they wouldn't sell them!) but for smaller runs it's something to consider. I've had issues with the cost per board exploding with some Nordic MCUs using very small pitches with double-rows in QFN packages.
@@PhilsLab yeah the weird thing is that they often put the specialised pins (like i2C) on the inner pins! Why not put the generic GPIOs there? They’re less likely to be needed, and it would probably encourage more people to use the part. 😁
@@Stabby666 I recall that the Nordic chips generally have pretty flexible pin assignments (almost any pin for a peripheral). Even then I find something like going from the aQFN-73 for the 52840 to an aQFN94 for the 5340 is harder because the former uses a 0.5mm pitch instead of a 0.4mm pitch. I would certainly prefer if Nordic also sold 0.8mm BGAs as well so that routing would be easy
@@monkev1199 That's interesting - is there a performance penalty for this (not so much i2C, but mostly SPI?) I'm sure I did check a few years ago but all the libs I was using assumed specific hardware pins as I recall. I know that the Espressif parts have reduced speeds when routed via the internal mux (SPI drops from 80 to 40mhz as a master).
The breaking away of the signal traces is something I didn't know. I have been putting them together. After watching your crosstalk video for differential pairs a while ago, I started thinking differently about signal traces.
Phil, thank you so much for sharing your experience! Another great material. But one small thing. I really miss your videos with KiCad or other free tools - I always enjoyed them. It's a bit unfortunate that many of us, including myself and the large community of hobbyists out there, can't afford an Altium license. There are so many hobbyists online, and I'm sure they appreciate content with accessible tools. Still, I really value the knowledge you're sharing! Thanks!
Thanks, Maciej! With my videos I try to make them as tool-agnostic as possible (with exception in this one, the small section on the IPC Compliant Footprint Wizard). So regardless of tool, you can implement what is shown in the video. Secondly, sponsorship luckily allows me to carve out time in my schedule to create these videos. And lastly, every year I try to cover the new KiCad releases in a long-form tutorial video. Those in combination with (pre-dominantly) tool-agnostic tutorials I hope are sufficient for anyone to follow along.
From what I've heard, the job market isn't great at the moment for juniors. At the time, what helped me the most was to have a portfolio of real-world, finished projects that I could attach to my application and then also have something to show and talk about during an interview. Good luck!
@@PhilsLab Yes indeed, I've heard/I've been told that as well and I'm witnessing it myself. It's curious given that many EU officials are calling for more engineering to be done in the EU, especially for defense. Clearly this need has not yet propagated to the job market. Germany is one of the candidate states for me, how do you like it there, working wise? Thanks a lot
I've easily got a job through freelancing. Someone wanted me to make a PCB and tried a few of my designs. He was happy with them and now I'm making them on a daily basis while still working on an engineering degree
Excellent presentation! I typically design the power layout first. I really like your concept of "intelligent compromise". On some of my designs it felt more like a "hail Mary", with performance checks done soon after the design is working. 1206 caps can be chosen at times, to get around some routing problems.
Thanks for watching! Coincidentally, some demo boards just came in with various antenna types that I'll be showing tuning methods for in an upcoming video!
Another excellent video Phil. One thing that wasn't mentioned (or that I missed) was via tenting and/or via plugging. This is helpfull for clearence and for situations like in 27:42
I know I'm posting a lot of comments here, sorry, but could you perhaps do a video on how you personally configure Altium, and what QoL features you're commonly using? I keep spotting little details in your videos (e.g. when you're routing, it's showing a kind of "fog of war" for where your traces would violate clearance DRC) that I'm not seeing when using Altium myself.
Hi Phil, Bit niche but would you ever consider doing a video on ultra high current e.g. 200A continuous PCB design say for example a power converter? Methods of carrying current and how to interface with MOSFETS? Thanks as always Doron
Thanks! This tutorial covers what I use to highlight my nets with different colours: www.altium.com/documentation/altium-designer/using-net-highlight-color-schematics-pcb
Nicely explained. As you say there are a lot of compromising weighing different requirements and options against each other to get an optimal layout. It'd be super interesting to see how much the placement of the decoupling capacitors actually matters in a real board. We all know that the inductance increases and the decoupling gets worse as the caps are moved away from the IC and the loop area increases. But how much does it affect the power quality right at the pad of the IC? I guess a guy like you have access to some really cool and nice equipment - could you maybe make a video about what actually happens when a decoupling cap is as close as possibly, maybe 10mm away, or even non existent on a microcontroller like the one you had in this video? EDIT: LOL, I should have watched one more minute of the video - you actually say that you are interesting in doing basically this :)
Thanks! I'm right in the process of making/ordering a demo PCB that will show the effects of various decoupling strategies (predominantly distance from IC pin, size of capacitor, ...).
It's a good design practice to balance the amount of copper on all layers. If your stackup is not symmetric with respect to copper distribution per layer, it can cause the PCB to warp during reflow. Thus it is easy to just fill in the remaining space with GND so that all layers have approximately an equal amount of copper. You have to ensure GND has the appropriate clearance to any high voltage or high speed digital traces (just to give 2 examples), but for most applications it's fine.
Hey Phil. I'm always thinking should I put via-s between decoupling capacitor and LQFP/QFN package or first to capacitor and then via down. I have used mostly first to capacitor and then via down. Would be nice video. As I understand when I have power plane then via down directly from LQFP/QFN would be better.
Yeah, it really depends on your PCB stack-up and routing. Definitely worth a whole video I'm currently planning for on decoupling incl. some tests/measurements.
@@PhilsLab I usually do 4 layers and signal-gnd-gnd-signal. If I can't route power on first or bottom layer(happens a lot) I just route power or use power planes on third layer.
Nice Video Phil ,I am just curious what is the bright yellow color on some traces signifies, as i am seeing none of the trace layer is chosen to be yellow.
Thank you! I select colours in the schematic editor which then transfer over to net colours in the PCB. For this particular video it was just to highlight different nets.
![เขามัทรี - เอ็กซ์ ศุภกฤต - จอนนี่มิวสิค [ Official MV ]](http://i.ytimg.com/vi/AS9ufKuQIVs/mqdefault.jpg)
Check out pms67.github.io/ if you would like to look through some of the PCB designs featured on this channel. I'll add more features/projects as time goes on! :)
That hint of tiredness in your voice when you said "vendors like to make their own package types" is something I feel in my bones. I've been digging into DrMOS parts (driver-integrated MOSFETs) and some of their pad layouts look like a box of pads that fell down the stairs. They frequently call them "QFN" but they're really LGA. The mechanical drawings are practically arcane heiroglyphs. I occasionally want to write "BE NOT AFRAID" next to them.
This video highlights an important consideration when choosing parts. The smaller QFN packages - especially with double rows, can introduce a STEEP price premium on the PCB manufacturing process. For example, needing to move down to sub-5mil tracks, and smaller vias, or even blind vias to access the pins. You can often find the exact same part in a slightly larger package that can save a lot of time and money per board, if you can spare a few extra mm in PCB size! There is obviously a point at which the smaller part becomes more viable when making large numbers of boards (otherwise they wouldn't sell them!) but for smaller runs it's something to consider. I've had issues with the cost per board exploding with some Nordic MCUs using very small pitches with double-rows in QFN packages.
Completely agree! And yeah, some of the Nordic parts have 'bizarre' footprints.
@@PhilsLab yeah the weird thing is that they often put the specialised pins (like i2C) on the inner pins! Why not put the generic GPIOs there? They’re less likely to be needed, and it would probably encourage more people to use the part. 😁
Exactly - I was going to make a KiCad video on that part, but then opted for one which doesn't require HDI...
@@Stabby666 I recall that the Nordic chips generally have pretty flexible pin assignments (almost any pin for a peripheral).
Even then I find something like going from the aQFN-73 for the 52840 to an aQFN94 for the 5340 is harder because the former uses a 0.5mm pitch instead of a 0.4mm pitch.
I would certainly prefer if Nordic also sold 0.8mm BGAs as well so that routing would be easy
@@monkev1199 That's interesting - is there a performance penalty for this (not so much i2C, but mostly SPI?) I'm sure I did check a few years ago but all the libs I was using assumed specific hardware pins as I recall. I know that the Espressif parts have reduced speeds when routed via the internal mux (SPI drops from 80 to 40mhz as a master).
The breaking away of the signal traces is something I didn't know. I have been putting them together. After watching your crosstalk video for differential pairs a while ago, I started thinking differently about signal traces.
Phil, thank you so much for sharing your experience! Another great material. But one small thing. I really miss your videos with KiCad or other free tools - I always enjoyed them. It's a bit unfortunate that many of us, including myself and the large community of hobbyists out there, can't afford an Altium license. There are so many hobbyists online, and I'm sure they appreciate content with accessible tools. Still, I really value the knowledge you're sharing! Thanks!
Thanks, Maciej! With my videos I try to make them as tool-agnostic as possible (with exception in this one, the small section on the IPC Compliant Footprint Wizard). So regardless of tool, you can implement what is shown in the video. Secondly, sponsorship luckily allows me to carve out time in my schedule to create these videos. And lastly, every year I try to cover the new KiCad releases in a long-form tutorial video. Those in combination with (pre-dominantly) tool-agnostic tutorials I hope are sufficient for anyone to follow along.
Do you have any advice for junior engineers entering the electronics industry? I'm finding it hard to find non-senior job openings on linkedin etc
From what I've heard, the job market isn't great at the moment for juniors. At the time, what helped me the most was to have a portfolio of real-world, finished projects that I could attach to my application and then also have something to show and talk about during an interview. Good luck!
@@PhilsLab Yes indeed, I've heard/I've been told that as well and I'm witnessing it myself. It's curious given that many EU officials are calling for more engineering to be done in the EU, especially for defense. Clearly this need has not yet propagated to the job market. Germany is one of the candidate states for me, how do you like it there, working wise? Thanks a lot
I'm self-employed with most of my contracts outside of Germany, so I'm afraid I can't really comment on 'normal' working conditions here!
Maybe starting an internship somewhere helps.
I've easily got a job through freelancing. Someone wanted me to make a PCB and tried a few of my designs. He was happy with them and now I'm making them on a daily basis while still working on an engineering degree
I like your capacitor symbols with the main specs in between the plates. Gonna have to start doing that myself.
I usually end up using the SnapEDA parts for my designs. I don't even bother checking whether the pins are matched correctly with the datasheet.
Watching now. Have a project with 3 QFNs onboard.
Excellent presentation! I typically design the power layout first. I really like your concept of "intelligent compromise". On some of my designs it felt more like a "hail Mary", with performance checks done soon after the design is working. 1206 caps can be chosen at times, to get around some routing problems.
Thank you for this great guide, Phil. Any news about the continuation of your chip antenna video about tuning with a NanoVNA?
Thanks for watching! Coincidentally, some demo boards just came in with various antenna types that I'll be showing tuning methods for in an upcoming video!
Another excellent video Phil. One thing that wasn't mentioned (or that I missed) was via tenting and/or via plugging. This is helpfull for clearence and for situations like in 27:42
I know I'm posting a lot of comments here, sorry, but could you perhaps do a video on how you personally configure Altium, and what QoL features you're commonly using? I keep spotting little details in your videos (e.g. when you're routing, it's showing a kind of "fog of war" for where your traces would violate clearance DRC) that I'm not seeing when using Altium myself.
This video is incredibly clear and full of practical examples-thank you!!
Thank you very much!
Another excellent video!!
Thank you very much, Patrick!
Thanks for making all those resources available!
Thanks for watching, Dustin!
@@PhilsLab I always watch. Thanks for making 😃
greatest resource for this subject as always. Thanks for the video
Thank you!
Hi Phil,
Bit niche but would you ever consider doing a video on ultra high current e.g. 200A continuous PCB design say for example a power converter? Methods of carrying current and how to interface with MOSFETS?
Thanks as always
Doron
This is excellent package specific advice. Thank you.
Thank you, Mike!
Perfect video as always :)
Thank you, Michael!
Great video.
Would be really nice if you could make a video on how to make colourful PCBs such as shown in the example. Thanks
Thanks! This tutorial covers what I use to highlight my nets with different colours: www.altium.com/documentation/altium-designer/using-net-highlight-color-schematics-pcb
Nicely explained. As you say there are a lot of compromising weighing different requirements and options against each other to get an optimal layout. It'd be super interesting to see how much the placement of the decoupling capacitors actually matters in a real board. We all know that the inductance increases and the decoupling gets worse as the caps are moved away from the IC and the loop area increases. But how much does it affect the power quality right at the pad of the IC? I guess a guy like you have access to some really cool and nice equipment - could you maybe make a video about what actually happens when a decoupling cap is as close as possibly, maybe 10mm away, or even non existent on a microcontroller like the one you had in this video? EDIT: LOL, I should have watched one more minute of the video - you actually say that you are interesting in doing basically this :)
Thanks! I'm right in the process of making/ordering a demo PCB that will show the effects of various decoupling strategies (predominantly distance from IC pin, size of capacitor, ...).
@ 32:21, did you do a ground pour on your signal layers besides having a dedicated inner layer for ground? And why?
It's a good design practice to balance the amount of copper on all layers. If your stackup is not symmetric with respect to copper distribution per layer, it can cause the PCB to warp during reflow. Thus it is easy to just fill in the remaining space with GND so that all layers have approximately an equal amount of copper. You have to ensure GND has the appropriate clearance to any high voltage or high speed digital traces (just to give 2 examples), but for most applications it's fine.
Another video is what we want.❤
Hey Phil. I'm always thinking should I put via-s between decoupling capacitor and LQFP/QFN package or first to capacitor and then via down. I have used mostly first to capacitor and then via down. Would be nice video. As I understand when I have power plane then via down directly from LQFP/QFN would be better.
Yeah, it really depends on your PCB stack-up and routing. Definitely worth a whole video I'm currently planning for on decoupling incl. some tests/measurements.
@@PhilsLab I usually do 4 layers and signal-gnd-gnd-signal. If I can't route power on first or bottom layer(happens a lot) I just route power or use power planes on third layer.
Kicad...stopped watchdog!
Nice Video Phil ,I am just curious what is the bright yellow color on some traces signifies, as i am seeing none of the trace layer is chosen to be yellow.
Thank you! I select colours in the schematic editor which then transfer over to net colours in the PCB. For this particular video it was just to highlight different nets.
@@PhilsLab Nice but when it is yellow when it is not, kindly make a little video on this feature!!!
Thanks again Phil
Thanks for watching!
At th-cam.com/video/hOamoJ15hmA/w-d-xo.htmlsi=yjJS1V46YdKgIj6v&t=1617 26:57 how do you make altium show areas where you cant route due to clearance?
While you're routing press Ctrl + W ('Display Clearance Boundaries').
@@PhilsLab THX
@@PhilsLab wait so after a press it oance to route i press it again , ok....
Love your vedios
Thank you, Rahul!