hey rob! how is it going? we miss your videos and live streams! you are doing really cool stuff and i enjoy your way of discovery, learning and even the mistakes that happen - those make it feel real! maybe even consider stuff like a discord server to let the community help/support you more directly! (maybe similar to how its working out for the wintergatan channel) i know it can be hard to stay motivated with those "hobby projects". with the "discrete" risc-v you chose a hard to reach target - its not important to actually finish it, but the act of trying is for sure worth it! -- and sharing it! hang in there and make even more friends!
To calculate the charge rate of a capacitor, I use the simplified formula t = from 3 to 5 * R * C, if I want the highest possible frequency, I choose a factor of 3, otherwise 4 or 5. In this case, the error fits into the temperature factor and the spread of the circuit parameters.
There is the 74HC688 that works with 3.3V. It is slow, in fact slower than the pull-up resistor implementation... With so many chips, the wiring will mostly dictate the speed, so I would not care too much about it. And at that rate the whole design can be 74HC with 5V supply, which is a better speed than 74HC at 3.3V. Also the fastest logic can be done with the 74CBT or 74CBTLV switches. They are especially good for the barrel shifter. They even have a 16-bit bus exchange part that could be used to reverse the direction of the shift. They have 5 Ohm resistance, 0.25ns propagation delay and 5ns switching delay, so even a ripple carry adder will have just 5ns overall, as the carry propagation is only limited by the 0.25ns delay. But again, given that it is a discrete design, the best speed is probably around 15MHz, for which 74HC at 5-6V is plenty. Maybe some critical parts like the adder using the faster 74AC283 in a carry select configuration could be used.
Where the heck am I? I'm still alive. I got side-tracked into working on code for programming an ATF150x chip, then I lost interest altogether. Sorry! I'm probably not going to pick this up again. Also, clearly I need to pick smaller projects to work on.
It's good to hear you're alive and ok. I can understand that you can run mad at things. Looking forward to you being ok, and looking forward to seeing you do something new and exciting.
RC time constant for 10k and 5pF is 50 ns. 2/3.3 is not far from 63% (one RC time constant), so pull up time is about 50 ns. As you say, there are plenty of variables (more inputs, output capacitance, trace capacitance, tolerance, temperature etc.), so a ballpark number is good enough.
Dear Robert. Sad your second attempt failed. It feels that both times you have had a good start and then things spiraled out of control, because you want to plan them out perfectionist. Maybe for another attempt at such a project try small iterations, can you build elements or part of a spec. Does it have to be the full RISC-V 32 ISA or is the reduced ok... . Your work was great and inspiring though, thank you very much.
Be very careful with your reasoning for 3.3V working with 5V logic... The value you want to consider is not VCC, but VOH_min. Every chip has a range of driving voltages, so you may have a case where a 3.3V chip has a VOH_min of VCC/2 which is 1.65V. In that case, the output logic level will be lower than the input voltage threshold on the 5V chip. I have run into this issue with connecting 3.3V chips to 2.5V IO banks on FPGAs. Using a CPLD is probably the better option here, though you are going to end up with quite a few of them.
15ns for the ATF1502ASV. There are GALs as fast as 4ns. The internal delays are quite low, so the layers don't contribute nearly as much as pin delays. Same for FPGAs.
@@obiwanjacobi 15ns pin to pin, so yes whole stack from input to output. That's the maximum delay for the -15 variant. The minimum is 3ns, so it's not bad. You should read the Pulitzer prize winning book titled "The Soul of a New Machine" by Tracy Kidder. He describes the design of the Data General Eclipse, which was probably one of the last discrete processor machines built. It was designed around newly released MMI PALs, which was somewhat revolutionary at the time. Now you can do it all in one smallish FPGA, designed on a weekend, easily clock at 100 MHz or more.
hey rob! how is it going? we miss your videos and live streams!
you are doing really cool stuff and i enjoy your way of discovery, learning and even the mistakes that happen - those make it feel real!
maybe even consider stuff like a discord server to let the community help/support you more directly! (maybe similar to how its working out for the wintergatan channel)
i know it can be hard to stay motivated with those "hobby projects". with the "discrete" risc-v you chose a hard to reach target - its not important to actually finish it, but the act of trying is for sure worth it! -- and sharing it!
hang in there and make even more friends!
Very cool! I especially enjoyed the explanation of the progression from PAL to CPLD including a description of the theory of operation.
I'm really sad, that this series seems dead... I was truly looking forward to the product!
Thank you for explaining the basics of CPLDs and their ancestors.
Don’t give up! We want to see you succeed!
To calculate the charge rate of a capacitor, I use the simplified formula t = from 3 to 5 * R * C, if I want the highest possible frequency, I choose a factor of 3, otherwise 4 or 5. In this case, the error fits into the temperature factor and the spread of the circuit parameters.
There is the 74HC688 that works with 3.3V. It is slow, in fact slower than the pull-up resistor implementation... With so many chips, the wiring will mostly dictate the speed, so I would not care too much about it. And at that rate the whole design can be 74HC with 5V supply, which is a better speed than 74HC at 3.3V. Also the fastest logic can be done with the 74CBT or 74CBTLV switches. They are especially good for the barrel shifter. They even have a 16-bit bus exchange part that could be used to reverse the direction of the shift. They have 5 Ohm resistance, 0.25ns propagation delay and 5ns switching delay, so even a ripple carry adder will have just 5ns overall, as the carry propagation is only limited by the 0.25ns delay. But again, given that it is a discrete design, the best speed is probably around 15MHz, for which 74HC at 5-6V is plenty. Maybe some critical parts like the adder using the faster 74AC283 in a carry select configuration could be used.
Where the heck am I?
I'm still alive. I got side-tracked into working on code for programming an ATF150x chip, then I lost interest altogether. Sorry! I'm probably not going to pick this up again. Also, clearly I need to pick smaller projects to work on.
Hey Robert!
Would you take a project that entails reverse engineering a chipset?
How much would something like that cost?
Thanks!
It's good to hear you're alive and ok. I can understand that you can run mad at things. Looking forward to you being ok, and looking forward to seeing you do something new and exciting.
RC time constant for 10k and 5pF is 50 ns. 2/3.3 is not far from 63% (one RC time constant), so pull up time is about 50 ns. As you say, there are plenty of variables (more inputs, output capacitance, trace capacitance, tolerance, temperature etc.), so a ballpark number is good enough.
Are you still planning on working on this?
Dear Robert. Sad your second attempt failed. It feels that both times you have had a good start and then things spiraled out of control, because you want to plan them out perfectionist. Maybe for another attempt at such a project try small iterations, can you build elements or part of a spec. Does it have to be the full RISC-V 32 ISA or is the reduced ok... . Your work was great and inspiring though, thank you very much.
Great stuff
Came for dragon
Stayed for very interesting problem solving discussion
Be very careful with your reasoning for 3.3V working with 5V logic... The value you want to consider is not VCC, but VOH_min. Every chip has a range of driving voltages, so you may have a case where a 3.3V chip has a VOH_min of VCC/2 which is 1.65V. In that case, the output logic level will be lower than the input voltage threshold on the 5V chip. I have run into this issue with connecting 3.3V chips to 2.5V IO banks on FPGAs.
Using a CPLD is probably the better option here, though you are going to end up with quite a few of them.
Looking forward to this series, are you okay rob?
Miss your videos, are you ok? :)
and next week never came :(
Hello! Robert, where are you? Are you ok?
finally found this again.. any updates on the LMARV-1 reboot, do you have any of the previous boards populated yet? (new ones?)
10:35 Is that an HP-48 series? That thing got me through college. RPN 4 life.
It is! HP-48SX. RPN peeps repreSENT.
@@RobertBaruch yes noticed, best choice at that time. Bought mine from EduCalc in NYC.
Nice video BTW, almost there?
Are you not working on your project now?
hey hi... so uh do you think you could help CuriousMarc with his hp 9825 somehow?
Any news?
Are you ok?
So what is the propagation delay of the CPLD with all its layers?
15ns for the ATF1502ASV. There are GALs as fast as 4ns. The internal delays are quite low, so the layers don't contribute nearly as much as pin delays. Same for FPGAs.
@@madhusiddalingaiah5301 15ns for one cell or for the whole stack from input to output?
@@obiwanjacobi 15ns pin to pin, so yes whole stack from input to output. That's the maximum delay for the -15 variant. The minimum is 3ns, so it's not bad. You should read the Pulitzer prize winning book titled "The Soul of a New Machine" by Tracy Kidder. He describes the design of the Data General Eclipse, which was probably one of the last discrete processor machines built. It was designed around newly released MMI PALs, which was somewhat revolutionary at the time.
Now you can do it all in one smallish FPGA, designed on a weekend, easily clock at 100 MHz or more.