i was very confused when my college professor explaing this subject but when i started watching ur lecturers inow am good enough in this so all credits goes to u mam "thank you sooo much for this"
Sabhi Lecture m abhi tak koi essa essa part nhi h jo dekhne k bad essa feel ho ki samjh nhi aa rha h proccessor after see every lecture very easy to learn every microcontroller or microprocessor thank you🙏🙏🙏
This is also an IC, vcc apply karane se on hogi. But there are multiple control signal that activates memory. This will become more clear when you will learn read write memory cycle
Ma'am min and Max mode you explained is really good but those same diagram we draw in exam will get full marks ? As it is as you pdf record,if possible then plss answer because my exam will start at 17 may
It seems you belong to Mumbai University. You can draw the same diagram. Diagram and explanation will give you full marks, some time they also ask to draw bus cycle diagram, so read question carefully. Best wishes
Do bus transciever recieves address?? That means u r showing the address travelling to the octal latch and bus transciever at a time But the bus transciever is responsible for only the data transfer And how the address is sent to memory to activate the location through the buses coming out from the latch or through the bus transciever???
![fellow fellow - พรุ่งนี้ไม่มีใครรู้ feat. INK WARUNTORN [OFFICIAL MV]](http://i.ytimg.com/vi/QP6JyjYx_W0/mqdefault.jpg)
![[Live] : ONE 169 วันนี้!! "อนาโตลี vs อูมาร์"](http://i.ytimg.com/vi/IK3YZVWuFJg/mqdefault.jpg)
You are doing greate efforts for students...salute to your work..❤
Thank you so much for your wonderful comment 😊
i was very confused when my college professor explaing this subject but when i started watching ur lecturers inow am good enough in this so all credits goes to u mam "thank you sooo much for this"
You are welcome 🤗. Thanks for your wonderful words. May you score good marks in this subject 👍
@@TheVertex-Engg-Lectures thanks mam for ur reply
Sabhi Lecture m abhi tak koi essa essa part nhi h jo dekhne k bad essa feel ho ki samjh nhi aa rha h proccessor after see every lecture very easy to learn every microcontroller or microprocessor thank you🙏🙏🙏
Thank you so much 😊 for your wonderful comment. Keep learning 👍
Great explaination ma'am
Made many students' life easier
Respect from Bangladesh ❤️
Thank you so much 😊 from India. Keep learning 👍
Mam you are great Now I am studying with your lecture. Thanks for this Lecture Playlist
You are welcome. I am glad that you liked it. Keep learning 👍
Mam Are the read and write bus diagrams same in this as well as the next video as you have described the diagrams two times are the different or same
Yes same. In the video of timing diagram it is explained with more clarity
mam what is the chip selection logic in minimum and maximum mode??
Can you please elaborate your question?
Our sir has given a one more block in diagram named cs logic .
BHE bar pin and a0 pin is connected to this block
THANKS
You are welcome. Thanks for always commenting 😊
Mam concept to pura smj agya kya iske according khi notes mil skte hai
So sorry notes can not be provided for copyright reasons
Mam is there is any english explain vdo for max mode
Can u rpy fast
Yes it is available in English playlist, check it
@@TheVertex-Engg-Lectures mam only min mode is there no max mode
@@muthulekshmi7345 check once again
@@muthulekshmi7345 ohh I guess I forgot to upload. Will upload it by tomorrow if video is ready
mam u teach in very nice way 😘😍
Thank you so much 😊
Understood bus cycle very clearly , watched many videos but they are just theory
thanks dear
Ma'am memory location ko activate kese krte hai so that receiving/transferring data us loc m ho paye?
This is also an IC, vcc apply karane se on hogi. But there are multiple control signal that activates memory. This will become more clear when you will learn read write memory cycle
@@TheVertex-Engg-Lectures Ok ma'am
Amwc write bus diagram mai apne nhi btaya kya hai mam ye
Advance memory write it starts early
Madam in max mode write operation how come DEN becomes 1 when the input given to it is zero
In max mode den is generated by bus controller 8088 and is active high but in minimum mode it is den bar and active low and generated by 8086.
@@TheVertex-Engg-Lectures thank you ma'am
Madam can you suggest best text text book to study for exams
@@shaikrehman3236 it depends on your syllabus
Add status kya hai mam
Please write your doubt in detail
@@TheVertex-Engg-Lectures mam jo bus diagram usme add status bhi hai vo kya hai
@@himanshudubey690 it indicates the duration in which address flows on address data multiplex bus after 3rd t state data flows on the same bus
Ma'am min and Max mode you explained is really good but those same diagram we draw in exam will get full marks ? As it is as you pdf record,if possible then plss answer because my exam will start at 17 may
It seems you belong to Mumbai University. You can draw the same diagram. Diagram and explanation will give you full marks, some time they also ask to draw bus cycle diagram, so read question carefully. Best wishes
Do bus transciever recieves address??
That means u r showing the address travelling to the octal latch and bus transciever at a time
But the bus transciever is responsible for only the data transfer
And how the address is sent to memory to activate the location through the buses coming out from the latch or through the bus transciever???
No bus transceiver is used for transferring and receiving data. I have shown data flow through 8286.
@@TheVertex-Engg-Lectures from where the address is sent to the memory through demultiplexed address bus?
@@kushkusa7473 yes
Madam can you please provide all 8086 microprocessor lectures in English
There are lectures in English check playlist
mam what is the meaning of last third AIOWC and IOWC?
Advanced input output write control and input output write control
@@TheVertex-Engg-Lectures ok mam
kindly share the ppt
Sorry, you can take screenshots