Sorry,there is a mistake...at r=s=1,both outputs will be 1 Sometimes due to nervousness aisi mistakes ho jaati hain Thanks to all those students jinhone carefully video watch kiya and mujhe mistake batai🙏🙏
mam in latches you have taken s and r compliment when making with nand gate but here direct using s and r..... for solving it we are taking nand gate with clock???
mam if Q(t)=1,S=0 and R=1 at 5:12 of video then the first output i.e, Q=Q'=1 hota hain uske baad Q=0 me change hota hai ,first case me jab dono 1 ata hai then wo toh invalid state ho jta hai?
Mam,when we will take both the values of S and R as 1 then invalid condition should occur in the latch and output of Q and Q' should be equal to 1 in that case. But why we are taking the outputs as 0 ?
Madam, please explain what will be behavior of this flip flop when in place of NAND gate (in the beginning which is receiving the clock pulse) AND gate is used and clock pulse is low, as in that case the inner latch will go in don't care state, can we consider it as flip flop is in "Inactive Mode".
Well if we use AND gate in place of NAND gate,then CP=0 will cause o/p of gate 1&2 to 0,then whatever may be the value of R and S, now gate 3 and 4 are still NAND gates,so input 0 to NAND gates result in 1 as output,so outputs of gates 3&4 will be 0,resulting in invalid state
@@aasaanpadhaai so, madam, is this invalid state considered as inactive state of this flip flop as in general we are considering invalid state as don't care and we use to consider don't care state in k map for finding characteristics equation.
Sorry,there is a mistake...at r=s=1,both outputs will be 1
Sometimes due to nervousness aisi mistakes ho jaati hain
Thanks to all those students jinhone carefully video watch kiya and mujhe mistake batai🙏🙏
THANKU SOOO MUCH 😘😘😘🥰🥰🥰🥰🤗🤗🤗
mam in latches you have taken s and r compliment when making with nand gate but here direct using s and r..... for solving it we are taking nand gate with clock???
mam if Q(t)=1,S=0 and R=1 at 5:12 of video then the first output i.e, Q=Q'=1 hota hain uske baad Q=0 me change hota hai ,first case me jab dono 1 ata hai then wo toh invalid state ho jta hai?
Mam,when we will take both the values of S and R as 1 then invalid condition should occur in the latch and output of Q and Q' should be equal to 1 in that case. But why we are taking the outputs as 0 ?
Mam flipflop or latches ki implementation bta dain
Mam which output we have to consider ? Q or Q bar
R 1s 1 case me 1 milega
Maam ek suggestion
Aap video ka thumbnail change jar dijiye views increase honge because your explanation is ossum 💯💯
Madam, please explain what will be behavior of this flip flop when in place of NAND gate (in the beginning which is receiving the clock pulse) AND gate is used and clock pulse is low, as in that case the inner latch will go in don't care state, can we consider it as flip flop is in "Inactive Mode".
Well if we use AND gate in place of NAND gate,then CP=0 will cause o/p of gate 1&2 to 0,then whatever may be the value of R and S, now gate 3 and 4 are still NAND gates,so input 0 to NAND gates result in 1 as output,so outputs of gates 3&4 will be 0,resulting in invalid state
@@aasaanpadhaai so, madam, is this invalid state considered as inactive state of this flip flop as in general we are considering invalid state as don't care and we use to consider don't care state in k map for finding characteristics equation.
It will be inactive state. Because this case does not arise due to possible input combinations.It arises due to low clock pulse. So CP should be high
@@aasaanpadhaai Thank you, mam.
I want to know yr education qualification
Last . ma 1 1 ANA CHAHIYEE Q AND Q COMPLEMENT KO 💔💔💔😒😒 MAM KIA KR RHI HO AP BNDA PIN CMNT KR DETA H K yha Sy GHALTI ho gaie h
Last case s=1&r=1me Q&Q-dono hi 1 aayenge 🙄🙄
wahi tho pta nhi yha kon sa logic laga hai
@@hriteshkumarsingh3582 it was mistake already told by ma'am in pinned comment🙂