132N. Integrated circuit biasing, current mirrors, headroom
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- เผยแพร่เมื่อ 2 มิ.ย. 2024
- Analog Circuit Design (New 2019)
Professor Ali Hajimiri
California Institute of Technology (Caltech)
chic.caltech.edu/hajimiri/
© Copyright, Ali Hajimiri - วิทยาศาสตร์และเทคโนโลยี
@23:00 One problem not mentioned in the BJT current mirror is the presence of the parasitic base resistor. The BJT that far away from the diode connected BJT, its base voltage is smaller due to the voltage drop across the parasitic resistor, and essentially the Vbe is smaller in contrast to the the nearest BJT whose Vbe is larger. Of course, this base voltage drop due to the parasitic resistance is very small due to the small base current and parasitic resistance. However, as the number of parallel connected BJT increases, and connecting another BTJ to provide the sum of all base currents @21:18, the voltage drop on base cannot be ignored as the current is proportional to the exponential of Vbe.
Machallah professor your type of teaching is very unique and genius, Alahmdolilah that your in academia and not in the industry so the generations can access to this genius explanations
Inutuitive Explanation for beta * ro / 2 for the cascode current mirror (you explain this at 56:50):
To understand this, we must introduce a different view on cascodes in general. You nicely described (in the previous lectures) the change of output resistance by cascoding. But here comes another explanation in handy: For the cascode current mirror, the upper current mirror forces same Vce over the lower current mirror, thus eliminating the Early effect. That elimination is the reason for the increase in output resistance. With this "new view" it becomes much easier to understand:
The upper right transistor still suffers from the early effect. We dont see it, because the low current mirror enforces constant current. But when Vce over the upper right transistor increases, it allows more current to flow which cannot flow because the lower current mirror forbids it. Instead, the base current of the upper right transistor reduces by almost the same amount Ic through the upper right tranistor increases. That's key observation: delta Ibase EQUALS delta Ic in this case. But the system is fed via a current source. This reduction in the upper rights base current adds mainly to the Ic from the left path and is mirrored to the right side when the lower current mirror "receives" it. So, in a "normal" or "simple" cascode, the base current reduction does not matter. It never hits anyhwere. But for the cascoded current mirror, this reduction in base current is reflected to the lower current mirror and there appears a second time, thus leading to ro * beta / 2 instead of a nice ro * beta.
Note how this DOES NOT happen for the casocdes you described in previous lectures. They were just set to some Vbias and any change in base current never hit anywhere.
Effectively, the red circular arrow you drew must run in the other direction, according to my explanation.
Edit: Keep on the great work. Greetings from Germany.
The fact that this video has no dislikes shows how good the explanations are
"dislikes" are automatically hidden by TH-cam. However if one person has clicked on "dislike" button then he have some problems.
@@stefano.adislikes used to be shown before they decided to remove that
@@stefano.a the time the OP posted the comment the dislikes were still operating
Thank you very much sir!
Keep making videos and enriching the electronics community.your insights and intuition make these videos an excellent watch.
If possible please upload some handouts or problem sets
big Hi from Algeria
.
Welcome to the channel.
are u algerian interested in analog ic design ?, if yes please give me your email
Hello Prof. I'm currently taking a class in analog integrated circuits but watching your lectures for additional insights, which you seem to provide a lot of. For instance, during our lecture on current mirrors, we didn't consider the fact we might be drawing too much current from the "golden source" and how that could be taken care of. I don't think I read something like that from the book I'm using (Analog CMOS by Razavi). I'm just wondering if you recommend another book that I read in tandem with Razavi's book.
Hello! I recommend the book
Analysis and Design of Analog Integrated Circuits, 5th Edition 5th Edition
by Paul R. Gray (Author), Paul J. Hurst (Author), Stephen H. Lewis (Author), Robert G. Meyer (Author)
Hello. I have been watching your course videos and I find them very good and useful . I was curious, what activities do the students have to do during the laboratory of your analog circuit design course? DO they do simulations or have to do a design project ?
Excellent !
00:04 Integrated circuit biasing is different from discrete design biasing due to economic and device properties.
02:06 Integrated circuits benefit from close proximity and batch processing for better matching.
06:35 Relationship between different types of transistors and current mirrors
09:07 Current mirrors allow replication and scaling of a reference current.
14:06 Parallel operation of bipolar transistors led to sequential failure.
16:18 The base-emitter voltage (VBE) of a bipolar transistor has a reverse temperature coefficient.
20:46 Using transistor beta to reduce base current in multiple stages
22:54 Biasing and current mirrors are specific to certain types of devices.
27:22 Choosing between different transistor connections based on advantages and disadvantages
30:16 The key aspect of a good current source is high output impedance.
34:27 To effectively generate and copy currents, an arbitrary three-terminal device should be more sensitive to V21 than V31.
37:02 Output resistance and limitations of current sources
41:15 Design parameters control integrated circuit performance.
43:28 Creating complementary mirror with PNP transistors
47:24 Using White's Law current source to scale down current in integrated circuits.
49:38 The output current can be calculated using the difference of two logs.
54:13 Introduction to cascode and cascode current mirror
56:37 Explanation of integrated circuit biasing and current mirrors
1:01:29 Cascode output voltage
1:04:33 Addressing the challenge of reducing the voltage to 2 delta Vgs in MOSFET circuits.
1:09:46 Solving problems one step at a time
Crafted by Merlin AI.
For the current mirror, why must we tie the base to the collector of the reference transistor? why not just pull up the base node to Vcc via a pullup resistor?
Here problem is with biasing voltage.we can use resistor divider circuit to provide required base voltage but problem is usage of resistors should not be encouraged,power dissipation may be one reason.If we go in same traditional way like voltage divider with vcc there is no point in using current mirrors.one more thing the resistors are temperature dependent.by means of connecting bases of transistors required voltage is provided.
Here current is also temperature dependent,so idea is one golden current source should provide current to remaing circuit.I think this golden current source is developed in a way such that it is not affected by external factors.This current source is made with BAND GAP circuit.
Could we put current source in between P and N MOS diode connected transistors that would be used as Vgs reference points for their respected MOS type transistors?
Theoretically you can. But how to implement a PVT insensitive current source between two diode connected MOS? It would be very complicated.
1:08:11 Would we have also biased the transistor in the middle branch to threshold so that just VT drops across it's gate and source?
Like:
Since at the gate of the transistor in the middle branch VG = 2VT + 2ΔVGS and we want the source votage of the same transistor to be VS = VT + 2ΔVGS.
Hence VGS =VG - VS = VT.
The connection of the lower transistor of the middle branch forces the same current as the current reference, thus it forces the gate source voltage of upper transistor to be VT+ΔVGS. If the there is only VT drop across its gate source as you said, the transistor is barely turns on (in subthreshold region), and it cannot draw the same current as current reference.
1:10:05 is the Id current in the middle branch wasted power?
i think it's power vs headroom(swing) tradeoff.
42:36 the axis are swapped
42:00 Effect of Length on Headroom and output resistance of current mirror