VLSI Testing &Testability||CMOS IC Testing||Fault Simulation||Design for Testability||Ad-hoc, BIST

[@Venuswir446]

Thank you sir very helpful

[@sasikala-ow2sm]

Clear Explanation sir
THANKYOU

[@vijayasree6762]

Thanks a lot sir, I understood the every topic what you explained sir 🙏

[@n.c.chanduprasanth135]

your welcome. Please do subscribe and share to your friends.
chanduprasanth.blogspot.com/
follow this blog you can get all materials/notes/interesting articles.

[@vijayasree6762]

Sure sir

[@vijayasree6762]

Will you please discuss about gate level testing and function level testing sir???

[@n.c.chanduprasanth135]

@@vijayasree6762 ok, i will discuss. Please do subscribe and share to your friends.

[@vijayasree6762]

Subscribed sir 😇

[@Fpg-x2s]

Sir
Thanks good teaching .
We can understand easily.
Regards
Gopal raju

[@n.c.chanduprasanth135]

thank you very much. Please do Subscribe

[@shivalenin7788]

Thank you 🙏 sir

[@mandadivishnulatha720]

Very much useful vedio 🙏❣️

[@sushmamandavilli3640]

Please upload full syllabus of ece R16 and r 18

[@worldvideocentre6958]

Not able to download notes and ppt from the link

[@qemmm11]

😁

[@sandeepmulagalapati4230]

Can I get complete notes of this subject sir

[@pattiknuth4822]

awful speaker. difficult to understand.

[@pencil_giftz]

Thank you sir