What I would like to know is if this standard could help multiple GPUs share a workload in a scalable and low latency way that would improve on what is possible with SLI or Crossfire.
Have some queries: 1. How does CXL achieve low latency? Is it by introducing the device biases and multiplexing three different sub protocols? 2. What do you mean by dis-aggregation? How does CXL solve this problem?
There is nothing special for low latency in the protocol, it's just the way you access data. For a DMA operation, instead of reading the DDR, you read the cache that has a lower read latency. It's a fake low latency characteristic.
Here are some additional resources in Semiconductor Engineering's Knowledge Center semiengineering.com/knowledge_centers/standards-laws/standards/compute-express-link-cxl/
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That was brilliant, and answers the questions in my mind before even asking (about using multiple accelerators). Thank you guys
Glad it was helpful!
Fantastic video, thanks for all your hard work Ed.
What I would like to know is if this standard could help multiple GPUs share a workload in a scalable and low latency way that would improve on what is possible with SLI or Crossfire.
Nice short tutorial ! I used to work few cubes from Gary at G*, he always explains simplified at any level. Thanks Gary.
Glad it was helpful!
Great video. Thank you.
Have some queries:
1. How does CXL achieve low latency? Is it by introducing the device biases and multiplexing three different sub protocols?
2. What do you mean by dis-aggregation? How does CXL solve this problem?
1. Low latency: In comparison to the existing cache/mem protocols PCIe link is much faster
2. Dis-aggregation of the workload from CPU to accelerators
There is nothing special for low latency in the protocol, it's just the way you access data.
For a DMA operation, instead of reading the DDR, you read the cache that has a lower read latency.
It's a fake low latency characteristic.
thanks
we can achieve Gen1 --> Gen3 speed without going to Gen5 in CXL ?
Yes...But it will, in application, defeat the purpose of high bandwidth
one query? CXL support Gen4 device ?
Yes. Gen3 and above
@@sumankumarpatra7115 : Native Gen3 device or it has to be Gen5 degraded to Gen3 ?
How to know full concept of CXL
Please suggest any one
Here are some additional resources in Semiconductor Engineering's Knowledge Center semiengineering.com/knowledge_centers/standards-laws/standards/compute-express-link-cxl/
@@SperlingMediaGroup Thank you so much i