Design of a Differential Amplifier 45nm CMOS Process in Cadence Virtuoso | Part One

[@siddhant-x8k]

Make more videos on CMOS Comparator, ADC, Latches, CMOS Inverter etc. Also, appreciate your way of putting everything on the excel sheet.

[@electronicechos]

Thanks, will do!

[@qemmm11]

I do not understand it 😊

[@SAhellenLily]

Very interesting 😊

[@boyiwu9227]

22:08 In equation (3.9), the sign of VTH of NMOS seems wrong?

[@Storytime1816]

Sir, can you share those notes? anydrive link or anywhere

[@shamanthks7218]

Can you please share the document Google Drive link in the description? Thanks in advance.

[@imldukk]

Sir, i have some question, where did you get muCox of components?
I've try many ways but they yield different values. Is there any solution for design by gm/Id. Thanks

[@electronicechos]

Described in this video at 8:10 and so on. Thanks

[@imldukk]

@@electronicechos Excuse me, but why you chose W/L = 10/10 for NMOS but 1/1 for PMOS when finding muCox.
Why not choosing 10/10 for both. Thanks.

[@TawsifTurjoeee]

how did you get the cadence virtuso

[@electronicechos]

N/A

[@hiepthaiba7801]

what an interesting video! can you give me a schematic? thank you very much!

[@qemmm11]

Which wafer fab is still using the .45nm process? I'm curious! 🤔
So hard😱 but it looks so funny 😊
Why not gm=2k(vgs-vt)
But it is gm=2*3.14*GBW*CL(master ot doctor Class😮) why

[@electronicechos]

I don't understand your question

[@kesavarao5400]

Sir can you tell SAR ADC

[@electronicechos]

Keep, eyes on my Channel. If i get free time then i will

[@kesavarao5400]

Tq sir