StarFive VisionFive2, Pine64 Star64, Milk-V Mars, Milk-V Mars CM/Lite, DeepComputing FML13V01, ... and on and on all featuring JH7110 CPU which is about as good as it gets for in-order general riscv64 computing from a variety of vendors and suppliers.
agreed. The first 10ish seconds are fine; then the video slowly gets passed by the audio. Maybe the video is stuttering or slowing down but the audio starts to lead the video, which I think humans are very sensitive to. Lagging 100ms is fine, but leading 100ms causes an uncanny effect.
Am I crazy or is the audio not synced properly? I got similar impression when I watched AMD-Intel collaboration video. Checked it on both TV and phone - same effect, it is very small but I'm pretty sure something is off...
People keep saying there's an issue, but I can't see it and no-one can physically show me there's a de-sync. Every time someone shows me their device, it works fine.
@@TechTechPotato This video and your last one are off for me, on Firefox on PC and also the Android TH-cam app. Much less evident on smaller screen though. Regardless, the information is what is what I want, and get, out of the video. So thanks as always. Very cool things happening with RISC-V, feels like its picking up pace.
The foundation has already been laid. At this point it's worth waiting if valid pushback is being given. It's not like we are going to have a new ISA within the next 100 years. This is kinda it. Whatever gets decided on is what is going to be used. It's kinda like how html or utf8 is what we will be using for the next 100 years. It's worth waiting to get the standard right since the only way we get a new standard is if the first standard is so bad everyone abandons it
This is indeed incredibly important, looking at the spec. I've been wanting someone to implement RV64GCBVH and beyond for a couple years, to consider it a real desktop core. Also UEFI. This goes above that. It's gonna take Atleast a couple years to come out on shelves though!
Profiles are not the problem holding RISCV back in GP core use. As of right now, vendors can't get their hands on performant DDR controller IP seemingly, PCIE controllers are buggy etc. You can have whatever profiles you like, but unless your workload runs entirely in cache and doesn't need GPU or high-perf NICs, you're dead in the water. This is entirely orthogonal to ISA concerns.
@@TheNefastor The PCIE spec is not closed. It's just that making a PCIE controller is difficult and time-consuming - it requires investment and, once completed, it needs to be sold to recoup that investment. Open source really doesn't work for VLSI/ASIC/etc - the potential of free contributions from a large pool of volunteer contributors is very small because they're just not very practical - all the software is proprietary and very expensive, the tapeout is going to cost millions and take years etc. I wish this were not so, but it is.
I took a look at the RNG instructions (since I may have something to do with the RNG instructions in X86). I see they fall into the trap NIST laid by ratifying SP800-90A and SP800-90B but leaving SP800-90C unfinished. So they've defined an SP800-90B like thing when really you want an SP800-90C like thing. So for a certifiable RNG you are left with software post processing to finish the job, while being at risk of 90C changing to make your post processing non compliant in the future. This is a problem if you need to publish a spec now. It's worth identifying the subset of BSI that is also RBG2 and RBG3 compliant against the most recent draft 90C and going for that (that is what RdRand and RdSeed in X86 does) and specifying that for RISC-V. Then you are pretty safe since I got verbal assurances from NIST that the xor and RS RBG3 constructions in 90C will remain in the finalized 90C spec.
Note that the profiles do not define the platform for a general purpose OS. The platform is implicitly defined via the SBI spec, which is driven by the BRS and PRS task groups (Boot/Platform Runtime Services), and by the actual implementation thereof, for which the spec still leaves some decisions open, e.g. which traps to delegate to S-mode and how to treat them otherwise.
Why is the official Standards document PDF hosted on a google drive link ? Not quite as shady as making Presidential Executive Orders over twitter, but...
SpacemiT K1 does support RVA22 in the most higher level, this does includes some hypervisor instructions as optional, hope its implemented there, this core can be found on Banana Pi BPI-F3, so its easy to access
Hey there, would love if you could make an explanation how it could impact things like tenstorrents 5 minion cores. Just it would be good if i could understand it without a cs/math education. Like, i know there will be extensions for advanced math stuff. And it was the breakthrough for most architectures (ppc altivec, x86 - mmx/sse)! do people like tenstorrent somehow do the vector stuff at a higher level and don't need it? Or is it gonna give them a jump?
With AI/ML you are not getting around vector instructions or other forms of executing math in parallel. However even in regular compute they are useful. Cryptography, de/en coding audio/video or calculating a reasonable large sum. This is also huge for the embedded market, as it makes more projects feasible.
I think the other thing that needs to be done is translation of different instruction sets, especially since X86 and ARM are pretty big, and compatibility would be an issue.
With Arm announcing that they are cancelling Qualcomm's Armv8 licence, I suspect at least a few companies will consider putting some development investment into RISC V.
Frankly, an even bigger obstacle to the masd adoption of RISC V at the desktop market and above, is the lack of a standard BIOS format. Withiut that, development of desktop systems becomes difficult for independent software companies.
there are 2 de facto standardized BIOS formats :). you either use u-boot as a BIOS (which will boot the linux protocol which is de facto standardized, or a subset of UEFI) or you use a more complete UEFI implementation like EDK2. and UEFI on risc-v is standardized. ACPI for risc-v is either standardized or soon to be standardized, but it needs hardware adoption, most hardware currently just uses FDT instead of ACPI and that's sorta-linux-specific-but-not-entirely. so basically your 2 options are UEFI (EDK2 or u-boot) + ACPI (no hardware support yet) or "copy whatever linux does"
Do you think there is any chance windows will be supported on this? Without this support, there isnt going to be a huge pickup. Even for embedded, too much hassle to change
The audio is synced but the way the sound comes out in speakers is weird. On my phone it seems to only come out through the bottom speaker and on my headphones it also sounds like it's only coming from one direction. I think its just an issue with your mic settings. Like other youtuber's voices sound "full and natural" while yours sounds like a flat dub edited in
It's really a minimalist design that is difficult to program and is inefficient with memory. But its simplicity is interesting. I would only use them for low-end embedded hardware projects.
IBM mainframe, Z for zero downtime. Roots go back to the 60's with System/360 & 370. Learn your COBOL and you can fit right in. You know when you see someone at a terminal in a store or government and it looks like they are still using DOS, nope that's 3270 terminal emulation.
@@maxwellsmart3156 not always, I still have some DOS programs I keep running for a business. 🙂 or maybe it should be. 😞 (honestly, easier than Windows)
New generations of Z mainframes are still being produced. Its about like labeling Zen5 an 8086. Z is popular with banking transaction processing and similar tasks.
@@maxwellsmart3156 Retailers are more likely using an as/400 later evolved/renamed into "system i" based on the 64bit Power platform. and available with its own dedicated OS, AIX, or RHELinux. Still quite reliable, but much cheaper than a Z system.
@@maxwellsmart3156 I miss typing into a mainframe with a custom hotkey set and just zoning out while hacking stuff in there. Only had that for like 4 weeks of my life but it was THIS less stressful.
the people who use riscv are using it because it is what they need if they could use arm they would and save 100s of 1000s of dollars in development costs i dont really see the point of building a whole new architecture and ecosystem in order to be arm without the couple of cents of licensing fees of the 60+ working groups therre are perhaps 2 that want this and we've known for years that they will eventually split away and do their own thing the reason it is such a slow process is because every company in the space vies to be the "standard" the only contender gauranteed to fail is the council of swiss bureaucrats who release these documents
RISC-V would make sense if ARM was ripping off customers like Nvidia is doing now with CUDA or Qualcomm did on their CDMA, but ARM hardly monetised their ISA or TSA. I dont see why anyone would change status quo
All I know that RISC-V was released as engineering emission avaiting feedback from user base. i seen no feedback, only endless What is RISC-V video. Did any of you actually install CMake and compiled something on it?
@@DS-pk4eh Arm is a company that designs cores and licenses the blueprints their ISA is just along for the ride, that business model has nothing in common with RiscV. There are companies that design RiscV processors and they would probably work with you to make a custom package with just the modules you want, but they probably won't release the rights to the design beyond the production of your chips. There may be some creative commons blueprints that you could start with (Probably used for educational purposes.) but I suspect they would be minimalist.
Why don't we get rid of 8, 16, 32 data types and all their instructions and just 64 bit datatypes such as long and double? By reducing the complexity of the processor and eliminating support for smaller data types, you could potentially free up more space on the chip for additional 64-bit transistors. These extra transistors could be used for various purposes, such as adding more execution units, increasing cache sizes, or implementing advanced features like vector processing or out-of-order execution.
These instructions are trivial to implement and take basically zero area, especially on little endian systems. They are also extemely widely used in every piece of software to save memory and would be very slow to emulate. For reference every character in this comment is an 8 bit data type.
The main problem with RISC V adoption is that *nobody has the option to license or buy a mature core.* The only options available for RISC V designs are low performance, I.e. ~10X slower than other other chips. Therefore RISC V has seen limited adoption, only in microcontrollers and computing contexts for limited resources.
My understanding is that Berkeley RISC served as a very abstract example of a RISC design for ARM to follow, and key characteristics of it were not implemented, like register windows. So I imagine the crux of “take out unnecessary instructions to improve speed” was the main thing borrowed. Interestingly they used their experience with the 6502 (a sucky ISA if ever there was one) as inspiration, eg. the relatively efficient interrupt handling in ARM1. The Wikipedia article on ARM covers some of this, though I remember (very vaguely) this being discussed back in school when we were given Archimedes as replacements for our Beebs.
And in terms of RISC-V my understanding it’s a continuation of MIPS, which is the Stanford take on RISC. Eg. It does not have register windows. Where and how the fork in the road where MIPS (Stanford) and SPARC (Berkley) happened I’m not quite sure, but ARM, as a British product from Acorn Computing, was very much on the periphery of “RISC happenings”.
I've been hearing a lot about this "RISC-V" thing for the last couple of years, but... I can't seem to find where to buy a laptop running on it. Will it ever materialize? And please, I don't talk about the microprocessor in my microwave - nobody really cares about that kind of things.
There's only one right now that's commercially available - the DC-ROMA (and DC-ROMA II). Part of the problem on that front is the lack of standardization - this helps that
This is exciting, can't wait to have a decently performant Risc-V SBC or Dev Kit
Well, there's the kendryte K210...
StarFive VisionFive2, Pine64 Star64, Milk-V Mars, Milk-V Mars CM/Lite, DeepComputing FML13V01, ... and on and on all featuring JH7110 CPU which is about as good as it gets for in-order general riscv64 computing from a variety of vendors and suppliers.
New K230 is better.
There is audio sync issues.
agreed. The first 10ish seconds are fine; then the video slowly gets passed by the audio. Maybe the video is stuttering or slowing down but the audio starts to lead the video, which I think humans are very sensitive to. Lagging 100ms is fine, but leading 100ms causes an uncanny effect.
ironically it results in the audio being synced up for me due to the latency of my Bluetooth earbuds lol
Am I crazy or is the audio not synced properly?
I got similar impression when I watched AMD-Intel collaboration video.
Checked it on both TV and phone - same effect, it is very small but I'm pretty sure something is off...
People keep saying there's an issue, but I can't see it and no-one can physically show me there's a de-sync. Every time someone shows me their device, it works fine.
Consistently not synched on Amazon tablet running Brave browser. TH-cam generally behaves ok there..
I think you're right. Uncanny valley 😂
@@TechTechPotato audio before video for me on youtube on google-chrome linux and youtube on LG OLED CX. audio is correct in the outro at the end..
@@TechTechPotato This video and your last one are off for me, on Firefox on PC and also the Android TH-cam app. Much less evident on smaller screen though. Regardless, the information is what is what I want, and get, out of the video. So thanks as always. Very cool things happening with RISC-V, feels like its picking up pace.
Always remember: standardization is better than perfection.
The foundation has already been laid. At this point it's worth waiting if valid pushback is being given. It's not like we are going to have a new ISA within the next 100 years. This is kinda it. Whatever gets decided on is what is going to be used. It's kinda like how html or utf8 is what we will be using for the next 100 years. It's worth waiting to get the standard right since the only way we get a new standard is if the first standard is so bad everyone abandons it
I can't imagine a world without fused-multiply-add vector operator. Alot of software depends on it so I'm glad they added it into the new standard
lol
If your chained multiplications and additions preserve the precision and are performed as fast FMA then there is no need for FMA
I think this has been in the vector extension for awhile now....
Shout out to all my DSP bros ❤
@@Eugensson not necessarily, you also need to be concise, less instructions means less memory usage, the equivalence is not direct.
This is indeed incredibly important, looking at the spec. I've been wanting someone to implement RV64GCBVH and beyond for a couple years, to consider it a real desktop core. Also UEFI. This goes above that. It's gonna take Atleast a couple years to come out on shelves though!
Profiles are not the problem holding RISCV back in GP core use. As of right now, vendors can't get their hands on performant DDR controller IP seemingly, PCIE controllers are buggy etc. You can have whatever profiles you like, but unless your workload runs entirely in cache and doesn't need GPU or high-perf NICs, you're dead in the water. This is entirely orthogonal to ISA concerns.
@paulie-g I didn't know that. I guess PCIe needs to become open source too now 😅
@@TheNefastor The PCIE spec is not closed. It's just that making a PCIE controller is difficult and time-consuming - it requires investment and, once completed, it needs to be sold to recoup that investment. Open source really doesn't work for VLSI/ASIC/etc - the potential of free contributions from a large pool of volunteer contributors is very small because they're just not very practical - all the software is proprietary and very expensive, the tapeout is going to cost millions and take years etc. I wish this were not so, but it is.
I took a look at the RNG instructions (since I may have something to do with the RNG instructions in X86). I see they fall into the trap NIST laid by ratifying SP800-90A and SP800-90B but leaving SP800-90C unfinished. So they've defined an SP800-90B like thing when really you want an SP800-90C like thing. So for a certifiable RNG you are left with software post processing to finish the job, while being at risk of 90C changing to make your post processing non compliant in the future. This is a problem if you need to publish a spec now. It's worth identifying the subset of BSI that is also RBG2 and RBG3 compliant against the most recent draft 90C and going for that (that is what RdRand and RdSeed in X86 does) and specifying that for RISC-V. Then you are pretty safe since I got verbal assurances from NIST that the xor and RS RBG3 constructions in 90C will remain in the finalized 90C spec.
What an incredible coincidence- I was JUST looking into the riscv spec literally hours before the press release.
Very excited to see this
The base 32 integer machine is readable in an hour or two. It's not terribly hard to make a four stage pipeline or so. I almost gave one working....
Pleaes do an interview with the Intel graphics driver team
Very cool, thx for the update! RISC-V is clearly growing on all fields👍
Note that the profiles do not define the platform for a general purpose OS.
The platform is implicitly defined via the SBI spec, which is driven by the BRS and PRS task groups (Boot/Platform Runtime Services), and by the actual implementation thereof, for which the spec still leaves some decisions open, e.g. which traps to delegate to S-mode and how to treat them otherwise.
Fantastic news! Here's to an open computing future!
Why is the official Standards document PDF hosted on a google drive link ?
Not quite as shady as making Presidential Executive Orders over twitter, but...
I did think that was weird as well.
SpacemiT K1 does support RVA22 in the most higher level, this does includes some hypervisor instructions as optional, hope its implemented there, this core can be found on Banana Pi BPI-F3, so its easy to access
I'm such a nerd geeking out on a CPU ISA but there is something exciting about RISC-V to me
Hey there, would love if you could make an explanation how it could impact things like tenstorrents 5 minion cores. Just it would be good if i could understand it without a cs/math education.
Like, i know there will be extensions for advanced math stuff. And it was the breakthrough for most architectures (ppc altivec, x86 - mmx/sse)!
do people like tenstorrent somehow do the vector stuff at a higher level and don't need it? Or is it gonna give them a jump?
With AI/ML you are not getting around vector instructions or other forms of executing math in parallel. However even in regular compute they are useful. Cryptography, de/en coding audio/video or calculating a reasonable large sum. This is also huge for the embedded market, as it makes more projects feasible.
Whatever happened to MIPS?
I think the other thing that needs to be done is translation of different instruction sets, especially since X86 and ARM are pretty big, and compatibility would be an issue.
Thinking of shortcuts instead of fallbacks is the way to go.
Now I want Windows on RISC-V. Anyone? Qualcomm?!
With Arm announcing that they are cancelling Qualcomm's Armv8 licence, I suspect at least a few companies will consider putting some development investment into RISC V.
hopefully not. CP/M and some new creations much better choice.
Frankly, an even bigger obstacle to the masd adoption of RISC V at the desktop market and above, is the lack of a standard BIOS format. Withiut that, development of desktop systems becomes difficult for independent software companies.
there are 2 de facto standardized BIOS formats :). you either use u-boot as a BIOS (which will boot the linux protocol which is de facto standardized, or a subset of UEFI) or you use a more complete UEFI implementation like EDK2. and UEFI on risc-v is standardized. ACPI for risc-v is either standardized or soon to be standardized, but it needs hardware adoption, most hardware currently just uses FDT instead of ACPI and that's sorta-linux-specific-but-not-entirely. so basically your 2 options are UEFI (EDK2 or u-boot) + ACPI (no hardware support yet) or "copy whatever linux does"
Do you think there is any chance windows will be supported on this? Without this support, there isnt going to be a huge pickup. Even for embedded, too much hassle to change
hopefully not. Much rather love to see CP/M and some new creations.
Is RVA23 supposed to be read "R Ve A" - or "R 5 A" - guess it stands for Risk Five Architecture 2023?
The former.
It's "Risc-V Applications profile"
Other profiles are M(icrocontroller) and those for custom B(uild)
RISK-V consumer laptops when?
Now! See DC-ROMA ... tablet and laptop only ~US $300
You're working on something in the background.....what is it ?
The audio is synced but the way the sound comes out in speakers is weird. On my phone it seems to only come out through the bottom speaker and on my headphones it also sounds like it's only coming from one direction. I think its just an issue with your mic settings. Like other youtuber's voices sound "full and natural" while yours sounds like a flat dub edited in
what is the difference between rva23 and rva22? Why is it special
RISC V looks like "design by committee" to me. And they have been prolific in creating committees.
I don't see RISC V flying for a long time.
ai generated profile pic lmao
It's really a minimalist design that is difficult to program and is inefficient with memory. But its simplicity is interesting. I would only use them for low-end embedded hardware projects.
full democratization of silicon
What is this Z cpu architecture mentioned at the beginning? I've never heard of it.
IBM mainframe, Z for zero downtime. Roots go back to the 60's with System/360 & 370. Learn your COBOL and you can fit right in. You know when you see someone at a terminal in a store or government and it looks like they are still using DOS, nope that's 3270 terminal emulation.
@@maxwellsmart3156 not always, I still have some DOS programs I keep running for a business. 🙂 or maybe it should be. 😞 (honestly, easier than Windows)
New generations of Z mainframes are still being produced. Its about like labeling Zen5 an 8086.
Z is popular with banking transaction processing and similar tasks.
@@maxwellsmart3156 Retailers are more likely using an as/400 later evolved/renamed into "system i" based on the 64bit Power platform. and available with its own dedicated OS, AIX, or RHELinux. Still quite reliable, but much cheaper than a Z system.
@@maxwellsmart3156 I miss typing into a mainframe with a custom hotkey set and just zoning out while hacking stuff in there. Only had that for like 4 weeks of my life but it was THIS less stressful.
All about that base... 🙂
the people who use riscv are using it because it is what they need
if they could use arm they would and save 100s of 1000s of dollars in development costs
i dont really see the point of building a whole new architecture and ecosystem in order to be arm without the couple of cents of licensing fees
of the 60+ working groups therre are perhaps 2 that want this
and we've known for years that they will eventually split away and do their own thing
the reason it is such a slow process is because every company in the space vies to be the "standard"
the only contender gauranteed to fail is the council of swiss bureaucrats who release these documents
RISC-V would make sense if ARM was ripping off customers like Nvidia is doing now with CUDA or Qualcomm did on their CDMA, but ARM hardly monetised their ISA or TSA. I dont see why anyone would change status quo
@@cwaddle Wouldn't you agree that ARM could change that at any second? It's not like we haven't seen it before.
All I know that RISC-V was released as engineering emission avaiting feedback from user base. i seen no feedback, only endless What is RISC-V video.
Did any of you actually install CMake and compiled something on it?
Just how it is complicated to create actual SoC ready to be made by some foundry using RISCV ISA?
same as any other IC.
riscV is just the software interface (instruction set), it says nothing about the physical design.
Three years and 70+ mln usd
@@andreyriabushenko3081 hmmm how about 10mil and 2 yrs?
@@mytech6779 i know that, but is there already a cpu design, like what arm is offering ? So no nees to start with just ISA
@@DS-pk4eh Arm is a company that designs cores and licenses the blueprints their ISA is just along for the ride, that business model has nothing in common with RiscV.
There are companies that design RiscV processors and they would probably work with you to make a custom package with just the modules you want, but they probably won't release the rights to the design beyond the production of your chips.
There may be some creative commons blueprints that you could start with (Probably used for educational purposes.) but I suspect they would be minimalist.
First 2 minutes the audio is 0.1% off with usual videos.
Why don't we get rid of 8, 16, 32 data types and all their instructions and just 64 bit datatypes such as long and double? By reducing the complexity of the processor and eliminating support for smaller data types, you could potentially free up more space on the chip for additional 64-bit transistors. These extra transistors could be used for various purposes, such as adding more execution units, increasing cache sizes, or implementing advanced features like vector processing or out-of-order execution.
These instructions are trivial to implement and take basically zero area, especially on little endian systems. They are also extemely widely used in every piece of software to save memory and would be very slow to emulate. For reference every character in this comment is an 8 bit data type.
The main problem with RISC V adoption is that *nobody has the option to license or buy a mature core.*
The only options available for RISC V designs are low performance, I.e. ~10X slower than other other chips.
Therefore RISC V has seen limited adoption, only in microcontrollers and computing contexts for limited resources.
Maybe the profile standardization is going to give manufacturers more trust now to invest more in performant hardware.
This will be the end. The end of everything :(
Isn't Arm technically derived from Risc?
"RISC" is a description of a style of instruction set. RISC-V is a name of a particular instruction set.
@@Pelicanzzz I know that, but I thought RISC-V was a direct descendant of Barkley's RISC which served as the basis for Acorn's ARM-1
My understanding is that Berkeley RISC served as a very abstract example of a RISC design for ARM to follow, and key characteristics of it were not implemented, like register windows. So I imagine the crux of “take out unnecessary instructions to improve speed” was the main thing borrowed. Interestingly they used their experience with the 6502 (a sucky ISA if ever there was one) as inspiration, eg. the relatively efficient interrupt handling in ARM1.
The Wikipedia article on ARM covers some of this, though I remember (very vaguely) this being discussed back in school when we were given Archimedes as replacements for our Beebs.
And in terms of RISC-V my understanding it’s a continuation of MIPS, which is the Stanford take on RISC. Eg. It does not have register windows. Where and how the fork in the road where MIPS (Stanford) and SPARC (Berkley) happened I’m not quite sure, but ARM, as a British product from Acorn Computing, was very much on the periphery of “RISC happenings”.
World needs new RISC chips like sparc,mips.
I've been hearing a lot about this "RISC-V" thing for the last couple of years, but... I can't seem to find where to buy a laptop running on it. Will it ever materialize? And please, I don't talk about the microprocessor in my microwave - nobody really cares about that kind of things.
There's only one right now that's commercially available - the DC-ROMA (and DC-ROMA II). Part of the problem on that front is the lack of standardization - this helps that
Talk dirty to me 😂
Lfg
Monolithic
Yay CCP!
Sync goddamnit.
I'm serious when I say this - no sync issues my side, or any of my friends on any of their devices.
@@TechTechPotato It's gammy for me and I haven't had a stroke.
@@TechTechPotatosync issues for me (also with a previous video of yours). iPad Mini 4.
It's a bit uncanny for me - it seems the audio is ever so slightly (less than a second) ahead of the video. I'm on an Android phone using the YT app.
It's off by like 100ms and it's only your videos