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Hi, your videos are really helpful, please try to post ques from your other interviews too..
in calculating max skew, in that hold equation you have mentioned only 2 gate delays we have 3 gates in data path so skew is Tskew
Because when doing hold analysis we choose the shortest path which gives us the least delay in the circuit, In our case it is the path from input A to the output seeing only 2 gates
We can implement schematic with 8 transistors as well. Take PDN as YPUN is Dual of PDNadd 1 invertor before final outputcan someone please verify?
can you tell us what all books we need to prepare from to understand these topics??
STA for nanometer designs by Bhaskar and Chadha
Hi, your videos are really helpful, please try to post ques from your other interviews too..
in calculating max skew, in that hold equation you have mentioned only 2 gate delays we have 3 gates in data path so skew is Tskew
Because when doing hold analysis we choose the shortest path which gives us the least delay in the circuit, In our case it is the path from input A to the output seeing only 2 gates
We can implement schematic with 8 transistors as well.
Take PDN as Y
PUN is Dual of PDN
add 1 invertor before final output
can someone please verify?
can you tell us what all books we need to prepare from to understand these topics??
STA for nanometer designs by Bhaskar and Chadha