Hi. Thanks a lot for the excellent lectures. I really appreciate it. I hope that you are doing well, I notice that the last lecture was at the time the COVID crisis started hitting worldwide. I will be more than glad if you could continue to this work. Again, thanks a lot.
The BAR programming you explained was very confusing and missed alot of contextual information. Request you to re-make this lecture again with more focus on context and detail.
If more than one endpoint is connected to bridge (or if only one endpoint is connected to bridge but it has multiple functions implemented each has its own memory map) in this case how the memory range is set in bridge .could you please explain that.
Hi Sir, Thank you for the detailed explanation. I got confused in type-0 header base address calculation After writing all ones to BAR-0 i will get the read value as 0xFFFF_F00E. what will be the start address and range for the above register. Please guide me
For IO base/LIMIT 8 bits[7:0]/[15:8] are used 4 MSB bits[7:4]/[15:12] are writable 4 LSB bits[3:0]/[11:8] are read only. [3:0]/[11:8] tells that IO base address lies in 16 bit address range or 32 bit address range Lets consider its in 16 bit address range then bits [3:0]/[11:8] will be 0. and if we configures bit [7:4]/[15:12] to 6 (4'b0110) then then IO base address /limit will be 16'h6000/16'h6FFF after concatenating for IO base [4'h6,12'h000] for IO limit [4'h6,12'hFFF] hope it helps
Hi. Thanks a lot for the excellent lectures. I really appreciate it. I hope that you are doing well, I notice that the last lecture was at the time the COVID crisis started hitting worldwide. I will be more than glad if you could continue to this work. Again, thanks a lot.
Thanks for taking time in going into such detail about BAR programming. Encourage you to contribute more such content
Nice lectures. 👍. Thank very much for initiating to put videos on pcie explanation and background work did for it. Waiting for next lecture.
The BAR programming you explained was very confusing and missed alot of contextual information. Request you to re-make this lecture again with more focus on context and detail.
Very good explanation, very helpful thank you
If more than one endpoint is connected to bridge (or if only one endpoint is connected to bridge but it has multiple functions implemented each has its own memory map) in this case how the memory range is set in bridge .could you please explain that.
We need next video, can you please take time and upload next topics on pcie? These are really helpful. Thanks
please make a video on low power LTSSM States behavior or let me know if there is some document. Thanks
Hi Sir,
Thank you for the detailed explanation.
I got confused in type-0 header base address calculation
After writing all ones to BAR-0 i will get the read value as 0xFFFF_F00E.
what will be the start address and range for the above register.
Please guide me
2^12 -4KB - 0xfffff000 -0xffffffff
i am not getting the calculation of i/o base starting and ending bits
For IO base/LIMIT
8 bits[7:0]/[15:8] are used
4 MSB bits[7:4]/[15:12] are writable
4 LSB bits[3:0]/[11:8] are read only.
[3:0]/[11:8] tells that IO base address lies in
16 bit address range or
32 bit address range
Lets consider its in 16 bit address range then bits [3:0]/[11:8] will be 0.
and if we configures bit [7:4]/[15:12] to 6 (4'b0110) then then IO base address /limit will be
16'h6000/16'h6FFF after concatenating
for IO base [4'h6,12'h000]
for IO limit [4'h6,12'hFFF]
hope it helps
Very good explanation Thanks
Can you please explain by taking an example of how end point device memory address range maps or lies within Host device Bar0 address range
At time 22:30 it is 2p24 - 2p4 = 2p20=1MB not 16 mb as ur saying.
Audio is very low.... can you please improve the audio vokume
Thanks for the feedback.Will update this lecture soon
@@pcie3823 Audio in your other 3 lectures was low as well but not as low as this one. Great lectures btw. Thanks.
Nice .
Plz share app name for screen and audio recording. Thanks
notability
@@soumitmitruka is this for apple device or android?
please cover other topic like data link layer and physical layer
Lecture are well explained, can i receive the pdf of the notes
Can you please make a video on physical layer and ltssm states please., Thank you sir.
Thanks Sir
Please sir make a video on PCIe ltssm States
15:56 16MB not 8MB
Can you please provide the pdf
Can you show in terminal ? Enough of theory.