at 12:06 for the adder, instead of * inside the sensitivity list can i write always@(a,b,c) ?? or should the output also be included??, if the output variables that is s,c is included , why? because the sensitivity list should contain variables that changes its value right??
You are absolutely right. If something changes and it affects some others then mention that one in the sensitivity list. Here (a,b,c) is enough. But we generally mention * so that you don't need to remember each and every variable that are changing if the list of variable is huge.
As per verilog rules, wire can't be used to assign value in a procedural block like always and initial. left side of assignment operator must be reg type else shows error. Every procedural block can store intermediate values and wire can't store a value as it's just a connection so reg is used inside a procedural block for assignment. Thanks.
In the real world every module works parallely. So every module gives output based on the input it gets from other modules. So when there is input from one module going into another module there will always be output. This process that is getting output only stops when input won't be provided from one module to another module. Initialsation is not required. Think inputs are coming from out side world , this is how real time code works. It is stopped when there is no input means a,b,c,d are no more changing. Hope it helps. Please let me know if I am able to clear your query.Thanks.
You implemented full adder before using continuous assignment and now you are using procedural blocks. Are they equivalent or different? When do we use procedural instead of continuous or we can use either?
Both provide the same result. Continuous assignments are parallel execution and always block execution is sequential if there is no data dependency.Thanks.
These could be any signal such as you touch your touch screen and now sensor responds to it and open your app. You press any switch and the output of switch excites something to work. So here touch sensor output or switch output can be in sensitivity list.Even here the input to sensor or switch can be declared in sensitivity list . Sensitivity means system is sensitive to these signals.So it's any signal which helps to activate a piece of hardware or software.
Sir, in mux code, assign is used before " sbar= (~s) " expression but not " out = (a $ sbar) | ( b $ s) " expression. My ques is, when I will use assign keyword and when not. I am confused here.
assign is used for combinational circuit means which don't depends on clock. It is like assigning right side things to left side and it's clock independent.
I have one doubt sir. Why we have to use reg? As you tell reg is store variable like flip flop. It's work like a memory. But we have to declare like Output e; reg e; Why we have declare e at two time?
Output is by default wire, if we declare output as reg then it's storing the data(memory element) and not just a port. output reg a // if we declare like this then no need of separate DECLARATION like output a; reg a;
Yes, so far only verilog and VLSI related content has been uploaded in this channel. There is separate playlist for it.( Today I have uploaded Google classroom for students which is out of VLSI field.This is uploaded as govt of India has asked the school to use Google classroom for students during this pandemic.so I uploaded as the situation demanded)
at 12:06 for the adder, instead of * inside the sensitivity list can i write always@(a,b,c) ?? or should the output also be included??, if the output variables that is s,c is included , why? because the sensitivity list should contain variables that changes its value right??
You are absolutely right.
If something changes and it affects some others then mention that one in the sensitivity list.
Here (a,b,c) is enough.
But we generally mention * so that you don't need to remember each and every variable that are changing if the list of variable is huge.
what a great job sir, this tutorial are the best I ever watch on YT about verilog. Greetings
from Spain
Thank you for your appreciation. Happy learning.
Best verilog tutorial in TH-cam .Thanks a lot
Nicely explained. Better than other TH-cam channel .
Yes, friend he had nicely explained the concepts....
Finally I found very good channel for verilog and I am requesting sir please post more videos on registers,counters,alus,multipliers,etc.
Thank you. I will upload the video tutorial that you have mentioned but it needs a little time
Yes, friend he had nicely explained the concepts....
God bless u..
Good one..
Really really nice 👏👏👏 best tutorial of verilog in TH-cam .
Thank you .
Very good video
Sir at 8: 18 time why does it give an error if we replaced reg by wire.
As per verilog rules, wire can't be used to assign value in a procedural block like always and initial.
left side of assignment operator must be reg type else shows error.
Every procedural block can store intermediate values and wire can't store a value as it's just a connection so reg is used inside a procedural block for assignment. Thanks.
you are saying any changes in the event a,b,c,d without initializing and when it gets stopped??
In the real world every module works parallely. So every module gives output based on the input it gets from other modules. So when there is input from one module going into another module there will always be output. This process that is getting output only stops when input won't be provided from one module to another module.
Initialsation is not required. Think inputs are coming from out side world , this is how real time code works.
It is stopped when there is no input means a,b,c,d are no more changing.
Hope it helps. Please let me know if I am able to clear your query.Thanks.
You implemented full adder before using continuous assignment and now you are using procedural blocks. Are they equivalent or different? When do we use procedural instead of continuous or we can use either?
Both provide the same result. Continuous assignments are parallel execution and always block execution is sequential if there is no data dependency.Thanks.
You can use either. But combinational ckt are implemented in a procedural block for bigger design.
sir what is that symbol after the sensitivity list(*) that you used at the last example(full adder)
Sorry, it's not a symbol,that's the crusor of the mouse |
thank you sir
sir, how the values in the sensitivity list changes
These could be any signal such as you touch your touch screen and now sensor responds to it and open your app. You press any switch and the output of switch excites something to work. So here touch sensor output or switch output can be in sensitivity list.Even here the input to sensor or switch can be declared in sensitivity list . Sensitivity means system is sensitive to these signals.So it's any signal which helps to activate a piece of hardware or software.
Thank you sir
Sir, in the mux code, can i write " assign sbar= (~s) " in the always block before or after " out = (a $ sbar) | ( b $ s) " expression ?
You can not write ASSIGN inside ALWAYS block. It is always outside.
Sir, in mux code, assign is used before " sbar= (~s) " expression but not " out = (a $ sbar) | ( b $ s) " expression. My ques is, when I will use assign keyword and when not. I am confused here.
assign is used for combinational circuit means which don't depends on clock.
It is like assigning right side things to left side and it's clock independent.
Thank you so much
I have one doubt sir.
Why we have to use reg?
As you tell reg is store variable like flip flop. It's work like a memory.
But we have to declare like
Output e;
reg e;
Why we have declare e at two time?
Output is by default wire, if we declare output as reg then it's storing the data(memory element) and not just a port.
output reg a // if we declare like this then no need of separate DECLARATION like
output a;
reg a;
Sir can't we write directly write ~s without declaring sbar in the example of mux2*1_bh
We can write with bracket like (~s)
can we have ppt of this video?
Are you upload all about the verilog topic?
Yes, so far only verilog and VLSI related content has been uploaded in this channel. There is separate playlist for it.( Today I have uploaded Google classroom for students which is out of VLSI field.This is uploaded as govt of India has asked the school to use Google classroom for students during this pandemic.so I uploaded as the situation demanded)
What will happen if I use assign out = a&b&c&d instead of putting it in an always block
When ever a or b or c or d changes 'out' is updated with new value immediately.The same can be done using always block.