Great talk David! There are several really good ideas in here. God help the cameraperson though, not showing slides at critical times was super annoying.
I got one of the tinyfpga bx boards when they came out, made a signal generator out of it for school. I love arduino projects and fpga's really open up the possibilities, just like you said!
I tried to start with FPGA programming, but didn't really get my head around it. I found the VHDPlus IDE and with the simple language, embedded libraries and other features it helped me a lot to make some cool projects :) Just in case someone has the same problem
A lot of problems with open source RTL arise from the code being the result of student projects at college, using some janky interface that no one uses. Silicon engineers use things like AMBA specs -AHB, AXI, APB and so on for on chip busses and that's what we use on FPGAs to hook up our designs in validation environments. For soft cores - look to the old 8 bit CPUs. They all have extensive, free SW and compiler support and they are very easy to design in HDL. Avoid verilog - it's old and not used in industry. We use System Verilog and VHDL. If your tools support system verilog, use it - it makes much more sense and has exceeded VHDL in recent years in terms of usability, although VHDL is fine if that's what you know. In terms of signaling protocols, most of what he asked for is standardized already, you just need to find the right standard. But there are many because the different needs are many. Avoiding protocols with tri state signaling is good - Things like I2C. They are tricky to implement well and it's a bear to trace what is going on on a scope. The req-ack protocol he showed is fine, because it's easy to trace on a scope and critically, req-ack protocols are tolerant to synchronizers in the control path, which is something you will need to deal with when hooking chips together. There are many good books on RTL design. It's worth investing some time with one to get over the 'digital logic design' hump - getting past student projects and onto real world systems that do useful things.
(1) They age quickly. Next year's FPGA is better than last. (2) It's useless without the tools and the tools are expensive. The demo boards that people use - generally the vendor does a deal with the FPGA vendor for access to a limited version of the tools (E.G. the Altera Quartus 'Lite' edition. (3) It's not really necessary. If you need one you can buy one and plug it into USB or on a PCi card.
Exactly, this has been solved. But people don't use the standard. Also, VHDL is open source HDL (used in aerospace as its less buggy) rather than Verilog.
When the speaker is talking about a slide, show the slide.
here's the slides: davidthings.github.io/spokefpga/hackaday_slides_2019_11_12/#/
Learning FPGA programming is is 10% learning verilog and 90% deciphering datasheets and application notes
It's frustrating that most of the time the slide isn't shown!
slides from David here: davidthings.github.io/spokefpga/hackaday_slides_2019_11_12/#/
Great talk David! There are several really good ideas in here.
God help the cameraperson though, not showing slides at critical times was super annoying.
I liked the revolutionary ideas the speaker put forward and the thirst for change in the ee and maker space - cool talk! Viva la revolution!
I got one of the tinyfpga bx boards when they came out, made a signal generator out of it for school. I love arduino projects and fpga's really open up the possibilities, just like you said!
Good talk. Explains the basics of FPGA well and explains what an FPGA "ecosystem" could look like with interface standards, verilog code libraries etc
I tried to start with FPGA programming, but didn't really get my head around it.
I found the VHDPlus IDE and with the simple language, embedded libraries and other features it helped me a lot to make some cool projects :)
Just in case someone has the same problem
This made me really excited for the field!
Thanks for the talk.
Good stuff.
A lot of problems with open source RTL arise from the code being the result of student projects at college, using some janky interface that no one uses. Silicon engineers use things like AMBA specs -AHB, AXI, APB and so on for on chip busses and that's what we use on FPGAs to hook up our designs in validation environments. For soft cores - look to the old 8 bit CPUs. They all have extensive, free SW and compiler support and they are very easy to design in HDL. Avoid verilog - it's old and not used in industry. We use System Verilog and VHDL. If your tools support system verilog, use it - it makes much more sense and has exceeded VHDL in recent years in terms of usability, although VHDL is fine if that's what you know. In terms of signaling protocols, most of what he asked for is standardized already, you just need to find the right standard. But there are many because the different needs are many. Avoiding protocols with tri state signaling is good - Things like I2C. They are tricky to implement well and it's a bear to trace what is going on on a scope. The req-ack protocol he showed is fine, because it's easy to trace on a scope and critically, req-ack protocols are tolerant to synchronizers in the control path, which is something you will need to deal with when hooking chips together. There are many good books on RTL design. It's worth investing some time with one to get over the 'digital logic design' hump - getting past student projects and onto real world systems that do useful things.
Really nice talk about designing friendly module communication!
Such a good talk! Fantastic and engaging :)
Are there slides?
He hasn't put the slides up yet, but will put them up eventually: twitter.com/davidthings/status/1198328523762651136?s=20
davidthings.github.io/spokefpga/hackaday_slides_2019_11_12/
Why don't we see FPGA's in motherboards yet? Some desktop applications could really take advantage of coding some logic into FPGAs I would imagine.
They are very power hungry. And they dont really add much value when your hardware is fixed, as in a PC.
@@nicolasbrusco1997 So why are they used as accelerators in datacenters? Power is a key factor datacenters keep an eye on.
(1) They age quickly. Next year's FPGA is better than last. (2) It's useless without the tools and the tools are expensive. The demo boards that people use - generally the vendor does a deal with the FPGA vendor for access to a limited version of the tools (E.G. the Altera Quartus 'Lite' edition. (3) It's not really necessary. If you need one you can buy one and plug it into USB or on a PCi card.
WTF...! This guy is great!
awesome!
Wishbone Interface?
Exactly, this has been solved. But people don't use the standard. Also, VHDL is open source HDL (used in aerospace as its less buggy) rather than Verilog.
How do I get into FPGA, where do I start
Is there any good tutorial online?
Udemy.com has some decent intro classes. This talk sucked even for experienced FPGA devs like me. Academics blow at just about everything.
💯💯💯💯💯
nice sound quality... smack much?