Thank you! This is gold. I really hope one day when time comes I will be able to pay You back (and people like you who provide knowledge publicly) by doing what you are doing for younger generations!!! Inspiring.
A zillion thanks for this and all your wonderful lectures, Professor. I had no background in electronics, started playing around for a small consulting work- in the way, came across your videos - got hooked and I am learning everyday - You are my best teacher from that other side of the hemisphere 🙏
Thank you professor, very much appreciated your efforts in preparing valuable lectures. I have watched many of your videos and they helped me very much. Thank you again, all the best, Paul
Thank you for this very informative and well presented lecture. I like the style and your writing of notes on the slides to go along with the lecture. I really appreciate that you ended with a summary of experimental results.
This videolesson i can watch over and over. That showing of all the circuits possible to reach the same goal, all with their pro&con and an excellent explaination, that gives so much, related ánd other, usefull knowledge. I love learning this way. Because learning it ís, ánd on a very high level, but its more of those superinterresting things and also more easy to follow! (more than every other source of knowledge that at least i could ever found before!)
Thank you professor for your simple way of explaining complex concepts. I have a question. The 2 inductor type bridgeless PFC has many advantages including a simple drive requirement. Can we use 3 parallel sets of these on three phase supply with the same output capacitor? Your comments will be very helpful. Thank you
Dear Sir, I am thankful to you for sharing us such an important comparison. I am right now working on the same design but with interleaved concept. As I see you have mentioned to use GaN FETs for the boost transistors which BTW are pretty competitive to any SiC or metal oxide counterparts. However as far as I have researched the reverse diode voltage drop is very high. I see you have not mentioned anything about them, Please let me know if I have misunderstood the GaN transistor in your video? In case it is correct than I would say that for the same example if we would have considered a metal oxide FET with almost near forward device characteristics and operate in CRM we would be able to more on the Body diode drop loss. Please enlighten
Hi , The third quadrant conduction of a GaN is indeed an issue, I am planning to prepare video on that. Meanwhile, in a nutshell: you need to keep the dead time as small as you can.
Thank you so much for this video! Could I use modern SiC MOSFET instead GaN for Critical Mode in Bridgeless Totem Pole? SiC MOSFETs are really fast and have faster diodes than Si MOSFETs. Control of SiC MOSFET should be simpler than for GaN.
Thanks a lot for the interesting lecture. I have a question regarding the switching losses of the totem pole PFC .. if we use the critical conduction control (in order to allow the negative inductor current to discharge Qrr and Coss to the load instead of the channel of the FET), do you think this way can improve the efficiency and get rid completely of the reverse recovery issues associated with Si MOSFETs? I've seen the CrCM control being used with GaN and SiC PFCs only but never saw it used with a totem pole PFC using Si FETs !
IN the early days totem pole APFC was built around Si nut in hard switching mode. For efficient BCM you need low rds(on) and fast switching which is the advantages of the WBG devices.
Thank you sir, great explanation as usual. I am designing something similar to totem pole 3 but using all Si mosfets. I plan to use about 50kHz switching for 1.5kw output and ccm control. To eliminate qrr and coss problems I have added an auxiliary circuit to make the synch boost switch always in zvs; so no qrr, no Coss and most importantly no GaN fets... What do you think about it? Thank you
Amazing design, i actually have rather frivolous use idea for it 6v/3w bicycle dynamo efficient boost and rectification, maybe it wasn't first thing to come in mind while creating this device, but it should work brilliantly for that purpose Main issue is my lack of skills to design useful circuit, idea is to boost and rectify low voltage, then step it down with off the shelf step down board, another question is cost, building 100$ circuit to charge my phone/lipo/nimh batteries during joy ride seem rather costly endeavour Also were thinking to forego inductor itself, as in my case dynamo itself might provide required inductance trough it's windings
At 5:04 you said "breakdown voltage" when you actually meant "forward voltage drop" (of a diode). I shouldn't be nitpicking, but a professor gave me a lower grade just because I didn't use a proper term. Otherwise, your videos are very valuable. I feel like I'm attending a university. ☺
Congratulations on this video. I would have a question for you. on a variable inductance using diode. Please let me know if this is of interest for you.
Any time current flaw thru the Body diode of mosfet, watch out for Qrr. Mosfet (even super junction CoolMos type) have nasty Qrr. Once the Body diode is triggered, it takes long time for recombination of storage charge, even after the gate is tuned on. That was the major failure mechanism in a Resonant topology and Synchronous rectifier topology. Infineon has recognized of this weakness of the mosfet, so they have come up with new series called "CFD7", if you are employing Resonant Topology. Or the better alternative is GaN or SiC mosfet. They have extremely low Qrr. I have very long experience with Resonant typologies, non-dissipative snubbers and lossless voltage clamps.
@@sambenyaakov GaN makes Bridgeless PFC (1PH or 3Ph) very efficient. When you use all the devices GaN fet (no diode), it will turn out to be Bridgeless PFC, it produce high PF even for light load, low harmonic distortion. higher switching frequency make magnetics smaller. If you are interested in contacting me, i am on Linkedin.
Hi Sam, The explanation was too good..u made it so simple. But I have one doubt in this. At 40: 00 time of this video you have explained about zvm with crm mode.. I need to know about the negative current..if that cycle is ( possitive half cycle of AC )..if there is negative current means, the potential of vline is close to zero or lesser than output....let say the DC link(output) is 400v and if the line voltage is 150 there maybe negative current. But the time u mentioned(dead Time) here vds2 is almost gone to 0v...if the line voltage is 0 there is a point ....otherwise it will only reduce to the input voltage level right....Does the voltage across the Get will goes 0 at that point...Please rectify me this issue. As I am currently developing a 11kw OBC...
Hi, I am not sure I understand your question, let me try answering to what I undestood. Once S1 is turned off there will be self commutation of the voltage and S2 will start conducting in reverse direction (before its gate is turned on) so the current of inductor will start to rise except for the point of zero input voltage.
@@sambenyaakov Thanks Sam, My question was at this dead time(before S2 is on). What is the actual reason of negative current?( I thinks that is because the output voltage is higher than the input ,hence the Coss of s1 will be charged to that limit only). The actual question has two parts...first is, during that commutation period, what will be the voltage at input ?. How will be the Vds across the mosfet will goes to to 0?.( If there is some input voltagte across the inductor ..I think the voltage across the mosfet will be same as the input voltage ) Please correct me if my assumption is wrong...I hope u understand the question...
Dear Prof. Thanks for making this Video. its very helpful. would you please give a lecture on critical inductance design for single phase and three phase bridge rectifier circuits with passive LC filter.
Very interesting and good understanable Video! I have one question: Why they are using normal Si-MOSFETs for S3 ans S4 in the Totem-Pole topology? Does it not improve the efficiency using GaN-Transistor, too? Or SJ-MOSFETs? Thank you in advance for your response.
Sam Ben-Yaakov So it's doesn't matter which technology to use, if its SiC or Si with Sj for S3 and S4. Its a question of cost reduction and eliminating the diods?
Hello prof. as usual great info. thanks for bringing useful & intuitive explanations. BTW- I guess it should say Border line on slide 35 instead of Boarder?
Hello professor, I wanna take one step further into the study of the EMI issue of bridgeless PFCs. Several literatures mention that though both circuits suffer from quite grave common mode noise, the bi-directional circuit offer better CM EMI performance than the totem-pole circuit, because "It has the advantage of offering a balanced input impedance that can improve EMI (compared to the totem-pole circuit)", as mentioned in TI's webminar white paper SLUP390 "Power Factor Correction (PFC) Circuit Basics". This verdict is in accordance with a project I've been working on lately. I can't figure out why, so could you please shed light on this phenomenon? I can't wait for your reply, thank you!
To be more precise, I can't see why the Totem-pole circuit failed to offer "a balanced input impedance". Both circuits, it seems to me, operates in a similar manner during both half cycles of AC input, "symmetrically".
@@sambenyaakov Thank you for your answer! But I have some follow up questions. Indeed, the inductor feeds different terminal alternatively, but the alternation is of a very low frequency (50Hz), why may this impact the CE test, which is of 150kHz-30MHz.
In fact this is the present project I'm working on for my master thesis. Thank you so so much for the rear knowledge. Meanwhile I have issues with simulations can you please do video on simulation with ltspice
Would it be possible with this type of configuration or the newer 6 fet design to do single stage isolation? Ie ac to dc with transformer using resonance? It strikes me that you should be able to switch these in such a way that you’re effectively speeding up the sinusoid using the inductor and capacitor with the switching and thus skip the entire flyback or other topology so you just have this and nothing else. Probably really complex timing but an ic or code in an mc that did this would result in pretty major gains I would think.
@@sambenyaakov no, just thinking out loud that the problem after pfc is you still have to run it through a transformer with another half bridge or similar. Thinking that the ideal design is that the pfc stage uses those fets to create the resonance in a transformer to get an isolated power supply in one step. Then it’s just a synchronous rectifier on the other side and you’re done. These power supplies that use these are way too complex which is why they’re constantly failing.
@@jameshancock There are solutions like that. E.g around a flyback converter. The down side is the issue of the bulk cap. In APFC you need a large energy storage. Moving it to the load side has very many disadvantaged. This is why this solution is used only for low power.
@@sambenyaakov I thought so too, but I did a search (can't post links here sadly) of a design that works for both a USB C 100 W charger, and with a slightly different ripple control mechanism a 3000W proof of concept EV Charger. (and they think it would scale to 22kW)
Very interesting video Dr. Yaakov. However, if CRM Mode is used for ZVS, why are GaN required any more? Isn't it beneficial to use normal cheaper Si Mosfets in CRM with ZVS ? I mean all the complexity with GaN gate drive is reduced and still efficient system can be designed right? Thanks in advance.
Hi Ravi, with CRM you get what I call pseudo ZVS at turn off. Losses will depend on how fast is the fall time of the current. GaN are much faster. This is why pridgless CRM PFC exhibit higher efficiency.
Prof. Sam, why is the first topology -dual boost PFC called as bridgeless topology ? It still has a diode bridge at the output side right? Also, the second topology - 2 phase PFC : this seems to be more like a dual boost since it has like two separate boost converters connected in parallel kinda fashion. So, cannot understand why the first one is named as "dual boost"?
At 46:20, when Is1 reduces to zero, why would the reverse recovery current in S1 body diode follow the inductor current ramp? There is no inductor in body diode and the capacitor current path
Dear Prof. In the Bridgeless Totem Pole 3 diagram at 32:30 minutes of video, the Silicon Power MOSFET S4 should be conducting in the reverse direction. Desirably, the current should flow through the MOSFET Channel (Source to Drain) and not the body diode. I am confused because that is not how power mosfet usually works. Could you kindly help me understand the same?
Shailendra, Si MOSFETs conduct both direction when turned on. So in this application you need to drive the MOSFETs synchronously with the mains frequency.
Hi, This is sort of "lost art" as recent designs apply soft switching, but for low switching frequency it is still valid. I will try to prepare a video on that.
Dr. Sam. 200kHz. Even with hard switched full bridge, the efficiencies achieved are 93-95%. 200-600W brick converters are all hard switched full bridge ( the output rectifiers are replaced with mosfets to achieve higher efficiency. Definitely a 12VDC fan is required to cool the components. These are usually 12 layer boards. www.ti.com/lit/ug/sluua95/sluua95.pdf
On Slide 25 Coss is used to estimate the losses, this is very wrong as Coss is very voltage dependent. Some manufacturer give a time related output capacitance which could be used, or better still, use the reverse recovery charge* voltage.
The slide is OK if the Coss is the so called "energy related capacitance". Send me an mail to sby@bgu.ac.il and I will send you additional information on that.
Dear prof. Don't you have any new considerations about the capacitor filtered input rectifier of any SMPS? I mean, all amazing development about SMPS haven't been inproving the bridge-capacitor of the SMPS's input which have the same techology as 60 years. Yes, you just show the "bridgeless" advancement, but what could be accomplished into an under 30W SMPS related of all this subject, where one bridgeless could call for circuit complications with no added volume reduction - these SMPS usually use a single switch? Comments are welcomed. Thanks for your lectures.
Not sure I have followed your questions. Power factor correction is required above some power level (depending on application) . A bridge rectifier followed by a capacitor has two high level of harmonics. Bridgless power factor corrector with GaNs has higher power density and higher efficiency as compared to a conventional APFC. A cascode bridgless APFC has 4 switched, 2 high frequency and 2 low frequency.
Sam Ben-Yaakov Dear professor. Yes, I used your explanation as comparation, contrast, to firmulare the question: what could be accomplished today in order to improve the power density of just the bridge+capacitor of a 30W SMPS? I guess that the answer would be "nothing ", but I would like your consideration about. B. R.
Thank you Sir, I appreciate really your presentation wow. Can you please send your email or whatsapp .I have some questions about this topology. Thank you very much.
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Thank you! This is gold. I really hope one day when time comes I will be able to pay You back (and people like you who provide knowledge publicly) by doing what you are doing for younger generations!!! Inspiring.
Thanks Stanislav for taking the time to write this. Comments like your keep me going. The enjoyment of sharing is my true payback
A zillion thanks for this and all your wonderful lectures, Professor. I had no background in electronics, started playing around for a small consulting work- in the way, came across your videos - got hooked and I am learning everyday - You are my best teacher from that other side of the hemisphere 🙏
Thanks. Happy to have you hooked😊
I can not find words to express thank you
For presenting content like this
🙂Thanks
Thank you professor, very much appreciated your efforts in preparing valuable lectures. I have watched many of your videos and they helped me very much. Thank you again, all the best, Paul
Thanks for comment. I appreciate it.
Thank you for this very informative and well presented lecture. I like the style and your writing of notes on the slides to go along with the lecture. I really appreciate that you ended with a summary of experimental results.
Thanks for comment.
This videolesson i can watch over and over. That showing of all the circuits possible to reach the same goal, all with their pro&con and an excellent explaination, that gives so much, related ánd other, usefull knowledge.
I love learning this way. Because learning it ís, ánd on a very high level, but its more of those superinterresting things and also more easy to follow!
(more than every other source of knowledge that at least i could ever found before!)
Thanks Rob
Such an excellent lecture, many thanks !
Thanks
Thank very much for expensive lecture and explanation 💝
Thank for comment. So young and already watching these videos?😊
Thank you professor. Wonderful explanation.
Thanks
Your work is impressive. You're really commited with the community.
Thanks for comment.
@@sambenyaakov seriously. Its difficult to find such good content in youtube. You are very porfessional and didactic
Thank you! I was just curious about pfc. But your video made my day.
😊
Great Lecture.Thank you Prof. Sam.
Thanks😊
Thank you so much for your lectures 🙏🏽
🙏😊
🙂🙏
Many thanks for such explanation. You made it simple!
👍Thanks
Thank you professor for your simple way of explaining complex concepts. I have a question. The 2 inductor type bridgeless PFC has many advantages including a simple drive requirement. Can we use 3 parallel sets of these on three phase supply with the same output capacitor? Your comments will be very helpful. Thank you
It will be difficult to combine the to a feed a single cap. Why not use Vienna rectifier?: th-cam.com/video/fNqXzZSzCwU/w-d-xo.html
Interesting - again I had a rough idea about these, but never really knew what made them tick
👍
Good explanation. Thank you.
Thanks
OUTSTANDING 👏🏻👏🏻👏🏻👏🏻
🙏
Dear Sir,
I am thankful to you for sharing us such an important comparison. I am right now working on the same design but with interleaved concept. As I see you have mentioned to use GaN FETs for the boost transistors which BTW are pretty competitive to any SiC or metal oxide counterparts. However as far as I have researched the reverse diode voltage drop is very high. I see you have not mentioned anything about them, Please let me know if I have misunderstood the GaN transistor in your video?
In case it is correct than I would say that for the same example if we would have considered a metal oxide FET with almost near forward device characteristics and operate in CRM we would be able to more on the Body diode drop loss. Please enlighten
Hi , The third quadrant conduction of a GaN is indeed an issue, I am planning to prepare video on that. Meanwhile, in a nutshell: you need to keep the dead time as small as you can.
@@sambenyaakov wow, indeed, that's the most simple&smart way to tackle this issue!
Thanks for this lecture. So with critical mode switching and ZVS the benefits of GaN (31:00) is not that much and Si can be used.
Even with ZVS the turn off requires fast switching to minimize V-I overlap.
@@sambenyaakov thank you.
Thank you so much for this video! Could I use modern SiC MOSFET instead GaN for Critical Mode in Bridgeless Totem Pole? SiC MOSFETs are really fast and have faster diodes than Si MOSFETs. Control of SiC MOSFET should be simpler than for GaN.
Yes, SiCs are faster than Si but wuth switching losses about 5 times greater than GaNs. But SiCs are more mature technology than GaN.
Thanks a lot for the interesting lecture. I have a question regarding the switching losses of the totem pole PFC .. if we use the critical conduction control (in order to allow the negative inductor current to discharge Qrr and Coss to the load instead of the channel of the FET), do you think this way can improve the efficiency and get rid completely of the reverse recovery issues associated with Si MOSFETs?
I've seen the CrCM control being used with GaN and SiC PFCs only but never saw it used with a totem pole PFC using Si FETs !
IN the early days totem pole APFC was built around Si nut in hard switching mode. For efficient BCM you need low rds(on) and fast switching which is the advantages of the WBG devices.
Very nice presentation - thank you!
Thanks
Thank you sir, great explanation as usual. I am designing something similar to totem pole 3 but using all Si mosfets. I plan to use about 50kHz switching for 1.5kw output and ccm control. To eliminate qrr and coss problems I have added an auxiliary circuit to make the synch boost switch always in zvs; so no qrr, no Coss and most importantly no GaN fets... What do you think about it? Thank you
ZVS is good bure if you want very high frequency ZVS and GaN is the best.
thanks for sharing information.very helpful...
Thanks. You are missing an inductor 😉
@@sambenyaakov haha indeed!
Amazing design, i actually have rather frivolous use idea for it
6v/3w bicycle dynamo efficient boost and rectification, maybe it wasn't first thing to come in mind while creating this device, but it should work brilliantly for that purpose
Main issue is my lack of skills to design useful circuit, idea is to boost and rectify low voltage, then step it down with off the shelf step down board, another question is cost, building 100$ circuit to charge my phone/lipo/nimh batteries during joy ride seem rather costly endeavour
Also were thinking to forego inductor itself, as in my case dynamo itself might provide required inductance trough it's windings
Thanks for conversation.
At 5:04 you said "breakdown voltage" when you actually meant "forward voltage drop" (of a diode). I shouldn't be nitpicking, but a professor gave me a lower grade just because I didn't use a proper term.
Otherwise, your videos are very valuable. I feel like I'm attending a university. ☺
Well, YOUR professor deserves a lower grade. Notations and definition are important but not more than substance. Thanks for comment.
Congratulations on this video. I would have a question for you. on a variable inductance using diode. Please let me know if this is of interest for you.
Yes, please send details to sby@bgu.ac.il
Any time current flaw thru the Body diode of mosfet, watch out for Qrr. Mosfet (even super junction CoolMos type) have nasty Qrr.
Once the Body diode is triggered, it takes long time for recombination of storage charge, even after the gate is tuned on.
That was the major failure mechanism in a Resonant topology and Synchronous rectifier topology.
Infineon has recognized of this weakness of the mosfet, so they have come up with new series called "CFD7", if you are employing Resonant Topology.
Or the better alternative is GaN or SiC mosfet. They have extremely low Qrr.
I have very long experience with Resonant typologies, non-dissipative snubbers and lossless voltage clamps.
Thanks for raising these important points
@@sambenyaakov
GaN makes Bridgeless PFC (1PH or 3Ph) very efficient.
When you use all the devices GaN fet (no diode), it will turn out to be Bridgeless PFC, it produce high PF even for light load, low harmonic distortion. higher switching frequency make magnetics smaller.
If you are interested in contacting me, i am on Linkedin.
Hi Sam,
The explanation was too good..u made it so simple. But I have one doubt in this. At 40: 00 time of this video you have explained about zvm with crm mode.. I need to know about the negative current..if that cycle is ( possitive half cycle of AC )..if there is negative current means, the potential of vline is close to zero or lesser than output....let say the DC link(output) is 400v and if the line voltage is 150 there maybe negative current. But the time u mentioned(dead Time) here vds2 is almost gone to 0v...if the line voltage is 0 there is a point ....otherwise it will only reduce to the input voltage level right....Does the voltage across the Get will goes 0 at that point...Please rectify me this issue. As I am currently developing a 11kw OBC...
Hi, I am not sure I understand your question, let me try answering to what I undestood. Once S1 is turned off there will be self commutation of the voltage and S2 will start conducting in reverse direction (before its gate is turned on) so the current of inductor will start to rise except for the point of zero input voltage.
@@sambenyaakov Thanks Sam,
My question was at this dead time(before S2 is on). What is the actual reason of negative current?( I thinks that is because the output voltage is higher than the input ,hence the Coss of s1 will be charged to that limit only). The actual question has two parts...first is, during that commutation period, what will be the voltage at input ?. How will be the Vds across the mosfet will goes to to 0?.( If there is some input voltagte across the inductor ..I think the voltage across the mosfet will be same as the input voltage )
Please correct me if my assumption is wrong...I hope u understand the question...
super helpful！Thanks！
🙏😊
Dear Prof. Thanks for making this Video. its very helpful. would you please give a lecture on critical inductance design for single phase and three phase bridge rectifier circuits with passive LC filter.
Thanks for comment. Will try.
Critical inductance? What is that??
Very interesting and good understanable Video! I have one question: Why they are using normal Si-MOSFETs for S3 ans S4 in the Totem-Pole topology? Does it not improve the efficiency using GaN-Transistor, too? Or SJ-MOSFETs? Thank you in advance for your response.
Not really. Super junction Si transistors have a pretty low Rds(on) but suffer from large capacitances which is not an issue for 50-60 Hz.
Sam Ben-Yaakov So it's doesn't matter which technology to use, if its SiC or Si with Sj for S3 and S4. Its a question of cost reduction and eliminating the diods?
Correct
Sam Ben-Yaakov thank you for the quick response
thank you Sir
Most welcome
Hello prof. as usual great info. thanks for bringing useful & intuitive explanations.
BTW- I guess it should say Border line on slide 35 instead of Boarder?
Hi Raanan, Thnks. Yes absolutely border. I guess this will be left now for millenniums.
Hello professor, I wanna take one step further into the study of the EMI issue of bridgeless PFCs. Several literatures mention that though both circuits suffer from quite grave common mode noise, the bi-directional circuit offer better CM EMI performance than the totem-pole circuit, because "It has the advantage of offering a balanced input impedance that can improve EMI (compared to the totem-pole circuit)", as mentioned in TI's webminar white paper SLUP390 "Power Factor Correction (PFC) Circuit Basics". This verdict is in accordance with a project I've been working on lately. I can't figure out why, so could you please shed light on this phenomenon? I can't wait for your reply, thank you!
To be more precise, I can't see why the Totem-pole circuit failed to offer "a balanced input impedance". Both circuits, it seems to me, operates in a similar manner during both half cycles of AC input, "symmetrically".
In the classic approach the inductor always feeds the plus terminal of output. In TP the inductor feeds alternately the plus and minus terminals.
@@sambenyaakov Thank you for your answer! But I have some follow up questions. Indeed, the inductor feeds different terminal alternatively, but the alternation is of a very low frequency (50Hz), why may this impact the CE test, which is of 150kHz-30MHz.
In fact this is the present project I'm working on for my master thesis. Thank you so so much for the rear knowledge. Meanwhile I have issues with simulations can you please do video on simulation with ltspice
Perhaps in the future
@@sambenyaakov thanks alot. With these experience of yours you will break down the simulation process completely.
At 14:40, why is that said there is a floating ground while D3 and D4 are in conduction?
Local ground and Neutral are not at the same potential
شكرا كثيرا
👍
Would it be possible with this type of configuration or the newer 6 fet design to do single stage isolation? Ie ac to dc with transformer using resonance? It strikes me that you should be able to switch these in such a way that you’re effectively speeding up the sinusoid using the inductor and capacitor with the switching and thus skip the entire flyback or other topology so you just have this and nothing else. Probably really complex timing but an ic or code in an mc that did this would result in pretty major gains I would think.
Not sure I followed you. Are you referring to any particular minute in video?
@@sambenyaakov no, just thinking out loud that the problem after pfc is you still have to run it through a transformer with another half bridge or similar. Thinking that the ideal design is that the pfc stage uses those fets to create the resonance in a transformer to get an isolated power supply in one step. Then it’s just a synchronous rectifier on the other side and you’re done. These power supplies that use these are way too complex which is why they’re constantly failing.
@@jameshancock There are solutions like that. E.g around a flyback converter. The down side is the issue of the bulk cap. In APFC you need a large energy storage. Moving it to the load side has very many disadvantaged. This is why this solution is used only for low power.
@@sambenyaakov I thought so too, but I did a search (can't post links here sadly) of a design that works for both a USB C 100 W charger, and with a slightly different ripple control mechanism a 3000W proof of concept EV Charger. (and they think it would scale to 22kW)
Very interesting video Dr. Yaakov. However, if CRM Mode is used for ZVS, why are GaN required any more? Isn't it beneficial to use normal cheaper Si Mosfets in CRM with ZVS ? I mean all the complexity with GaN gate drive is reduced and still efficient system can be designed right? Thanks in advance.
Hi Ravi, with CRM you get what I call pseudo ZVS at turn off. Losses will depend on how fast is the fall time of the current. GaN are much faster. This is why pridgless CRM PFC exhibit higher efficiency.
Thank you
👍🙏
Hi prof, I would like to study the Qrr effect in the Ltspice. is it poosible ?
It is possible if the models are good. Some are, some are not.
Prof. Sam, why is the first topology -dual boost PFC called as bridgeless topology ? It still has a diode bridge at the output side right?
Also, the second topology - 2 phase PFC : this seems to be more like a dual boost since it has like two separate boost converters connected in parallel kinda fashion. So, cannot understand why the first one is named as "dual boost"?
Hi Dinesh
Please indicate the slide number or minute in video you are referring too.
nice job
At 46:20, when Is1 reduces to zero, why would the reverse recovery current in S1 body diode follow the inductor current ramp? There is no inductor in body diode and the capacitor current path
46:20 is the end of video
Please share a video on close loop control technique of totem pole pfc
Good subject. Will try.
Dear Prof.
In the Bridgeless Totem Pole 3 diagram at 32:30 minutes of video, the Silicon Power MOSFET S4 should be conducting in the reverse direction. Desirably, the current should flow through the MOSFET Channel (Source to Drain) and not the body diode. I am confused because that is not how power mosfet usually works. Could you kindly help me understand the same?
Shailendra, Si MOSFETs conduct both direction when turned on. So in this application you need to drive the MOSFETs synchronously with the mains frequency.
There is no application note which talks about hard switched full bridge. I only see ZVS phase shifted full bridge application notes
which controller can be used for bridgeless topology?
You can use just about any controller plus some logic. The problem is isolated current sensors. For borderline operation digital control will be best.
Dr. Sam: Can you please make a video on hard switched full bridge DC-DC converter ( 36V-72Vin: 12Vout)?
Hi, This is sort of "lost art" as recent designs apply soft switching, but for low switching frequency it is still valid. I will try to prepare a video on that.
Dr. Sam : hard switched full bridge is currently used in Telecom bricks (12Vout , 36V-72Vin)
Thanks. What is the switching frequency used?
Dr. Sam. 200kHz. Even with hard switched full bridge, the efficiencies achieved are 93-95%. 200-600W brick converters are all hard switched full bridge ( the output rectifiers are replaced with mosfets to achieve higher efficiency. Definitely a 12VDC fan is required to cool the components. These are usually 12 layer boards. www.ti.com/lit/ug/sluua95/sluua95.pdf
www.ti.com/lit/an/snva628a/snva628a.pdf (LM5045)
Dear sir,
Please make a video on 3 phase bidirectional PFC
Will try
@@sambenyaakov Thanks a lot!
On Slide 25 Coss is used to estimate the losses, this is very wrong as Coss is very voltage dependent. Some manufacturer give a time related output capacitance which could be used, or better still, use the reverse recovery charge* voltage.
The slide is OK if the Coss is the so called "energy related capacitance". Send me an mail to sby@bgu.ac.il and I will send you additional information on that.
How can trr be expressed in "pf"?
Please indicate to which slide number or minute in video are you referring?
@@sambenyaakov My apologies. I meant slide # 25 at 29m 23s. trr is expressed as 150ns for Si but 2pF for GaN.
Dear Sir, could you please please explain partial pfc
www.dientuvietnam.net/forums/forum/%C4%90i%E1%BB%87n-t%E1%BB%AD-%E1%BB%A9ng-d%E1%BB%A5ng/%C4%90i%E1%BB%87n-t%E1%BB%AD-c%C3%B4ng-su%E1%BA%A5t/1704907-s%C6%A1-%C4%91%E1%BB%93-ups-santak-c3k-kh%C3%B4ng-hi%E1%BB%83u-c%C3%A1i-c%E1%BA%A7u-diode-%C4%91%E1%BB%83-l%C3%A0m-g%C3%AC/page8
Dear prof. Don't you have any new considerations about the capacitor filtered input rectifier of any SMPS? I mean, all amazing development about SMPS haven't been inproving the bridge-capacitor of the SMPS's input which have the same techology as 60 years. Yes, you just show the "bridgeless" advancement, but what could be accomplished into an under 30W SMPS related of all this subject, where one bridgeless could call for circuit complications with no added volume reduction - these SMPS usually use a single switch?
Comments are welcomed.
Thanks for your lectures.
Not sure I have followed your questions. Power factor correction is required above some power level (depending on application) . A bridge rectifier followed by a capacitor has two high level of harmonics. Bridgless power factor corrector with GaNs has higher power density and higher efficiency as compared to a conventional APFC. A cascode bridgless APFC has 4 switched, 2 high frequency and 2 low frequency.
Sam Ben-Yaakov
Dear professor.
Yes, I used your explanation as comparation, contrast, to firmulare the question: what could be accomplished today in order to improve the power density of just the bridge+capacitor of a 30W SMPS? I guess that the answer would be "nothing ", but I would like your consideration about.
B. R.
Thank you Sir, I appreciate really your presentation wow. Can you please send your email or whatsapp .I have some questions about this topology. Thank you very much.
sby@bgu.ac.il
13:45
16:05
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