Lecture 28. Memory Consistency and Cache Coherence - Carnegie Mellon - Comp. Arch. 2015 - Onur Mutlu

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  • เผยแพร่เมื่อ 28 ธ.ค. 2024

ความคิดเห็น • 7

  • @lagaleradelconejo5005
    @lagaleradelconejo5005 4 ปีที่แล้ว +4

    1:05:45 empieza a hablar de coherencia de caché

  • @hariprasath6589
    @hariprasath6589 4 ปีที่แล้ว +1

    Sir, the lectures are great , is there any way we could get access to LAB assignments? I think that will give us more holistic way to learn this course, Thanks a lot

  • @shraddheshbhandari8740
    @shraddheshbhandari8740 8 ปีที่แล้ว

    I have a feeling slide number 28 is wrong. The third global order mentioned - AXYB will result in a deadlock i.e. none of the other threads would forward and keep retrying for ever. Is it so?

    • @CMUCompArch
      @CMUCompArch  8 ปีที่แล้ว +9

      The answer depends on what is in the "else" block. I would encourage you to think about it. Note that the goal of this example is not to demonstrate how to ensure livelock freedom in synchronization. The goal is to show what are acceptable and unacceptable global orderings under the definition of sequential consistency. Higher level synchronization primitives that enable livelock freedom can be built on top of sequentially consistent orderings.

    • @shraddheshbhandari8740
      @shraddheshbhandari8740 8 ปีที่แล้ว +9

      Yes, that makes sense. I overlooked the significance of the else construct in this case. Thank you so much. I really appreciate the effort taken to answer this here. I am really grateful to these lecture series. They are really good. Thank you.

  • @legendaryLoai
    @legendaryLoai 8 ปีที่แล้ว

    I do not understand how updates could be useless, I mean that if you do not update the other processor would have wrong not up to date values

    • @CMUCompArch
      @CMUCompArch  8 ปีที่แล้ว +8

      An update could be useless if the processor does not read the updated cache block before the cache block gets evicted or before another update to the block.