Great video; thanks for pointing out a useful tool. An issue that I have with such tools/spreadsheets is they don't provide any guidance to inexperienced designers as to realistic values for the input parameters. Most notably they typically seem to indicate that very low switching losses can be achieved as a result of unrealistically high switching rise and fall times. Eg. I tried the tool for a 18V to 12V/8A synchronous buck at 100kHz with a 33uH inductor and a CSD17579Q5A for the switch FET. I chose 5.8ohms for the total driver resistance (1 ohm driver, 1.8ohm FET Rg + 3ohms gate resistance) and it calculated a mere 82mW switching loss due to switch rise and fall times of 7ns and 6ns. Ok, 5.8 ohms is rather low but I'd expect that achieving such speeds would be *very* optimistic due principally to stray inductance, especially the FET's source inductance. My gut feeling is that 25ns is an ambitous but achievable target but I don't have any real experience to back that up. I know you've done videos on MOSFET switching but it would be great if you could cover the topic in a bit more detail including what are realistic switching speeds that can be achieved without heroic design and layout skills and EMI considerations. I've done a fair bit of searching but found very little hard information; plenty of videos showing the switching scope traces, but either they use very slow switching times (probably because capturing fast transistions requires expensive scopes and probes) or the timebase is too slow to make any reasonable estimates of the rise/fall times. You could also cover the benefits/tradeoffs to paralleling smaller switch FETs, rather than using a single larger device, to reduce the dI/dt rates of each FET and thus reducing the effects of stray inductances. Also it would be helpful if you could suggest typical MOSFET stray inductance values for common packages as they are rarely specified in the datasheets. [Edit] Finally, to what extent are the speed, and thus efficiency benefits of GAN FETs the result of the very low inductances of their special packages rather than their lower gate charge?
Quite a complex question, but I will try to somehow answer, at least partly - you can get a first idea of a transistors switching speed from the datasheet - usually it has some sort of values given that where practically measured using the test fixture - for the CSD17579Q5A you get 1n/7n fall/rise. Anyway, at 100KHz I would expect switching losses to be small, so the ~82mW value does not seem all that absurd. At this switching frequency, the biggest losses will be conduction. Anyway, you might find a transistor spice model and just create a basic simulation to get a better estimate, even if that will not split the losses into switching and conduction. Regarding package/trace inductance, a rule of thumb is 1nH/mm, its not perfect but its a start. However, at 100KHz, package parasitics are usually not specified since these are not the main contributor - layout and interconnections will be providing most of the issues.
@FesZElectronics Much appreciate your response. Power stage designer defines tr and tf to include the time when the FET d-s current is transitioning *plus* the Vds rise/fall times (ie. when losses occur). Following your suggestion I tried LTSpice using a BSG0811ND (very similar switching specs to the CDS part). The switching loss was 48mW with tr/tf = 4.7ns/5.5ns. These closely matched PSD's calculated 5.5ns/4.7ns. Trise and tfall were 2.8/3.0ns However adding 3nH parasitic FET source pin inductance quadroupled the sw loss to 195mW with tr/tf = 15.5/16ns. Rise and fall times were little changed to 3.7/2.9ns. I can't remember where I read the 3nH value for a D-PAK. I'm not sure how easy it would be to limit the stray inductance to even 3nH in a real implementation, hence my question as to how realistic tools like PSD are when it comes to switching speed - in the tool you can increase the driver voltage and reduce the driver resistance to 0 to suggest arbitrarily fast switching speed but in reality I assume limits arise due to the FET's dV/dt and dI/dt limits, EMC considerations and especially the stray inductances; I have no real world experience and am wary of simulations limitations hence my question. The problem with so many educational papers/blogs/videos is they teach the principles but rarely provide real world 'reasonable' numbers. Also note the TI FET D/S specs are for an impractical 0 ohm driver. I'm not sure how they could have tested that!
As someone that just completed an LLC design based on an ST Micro reference design, I feel your pain. Without going into details, I can say generally what you are asking is about the “magic” of pcb layout. These fine details are kind of an engineering IP of the designer if you will. I suggest you get the basic reference pcb design (buy the kit) and study the layers in detail. Expect several rev level changes as your board evolves. Or pay to have the layout done by a competent designer which has vast experience in your target end device. These guys are not just graphics people. Many are EEs. Just because they have done smps, this is no longer enough experience. They need to know your target chip. Should you decide to go on your own, the Altium videos on TH-cam regarding smps layout are invaluable. If you go this path, only use a target device which has a reference design offering. Most of the newer devices are basically a micro controller not a power management chip. Mixed signals of low amplitude (600mv)combined with high dv/dt (400vdc) are a special trick. When in one 16 lead soic. Pfc and half bridge in one device.
@@frnkbooth6871 Thanks for your helpful insights. My view is that designing a state of the art efficiency hard switching converter likely requires super-hero design skills, tools, long experience and cutting edge devices. However I'm sure that most competent engineers could design a switching regulator with moderate efficiency and with help even get it through EMI/EMC certification - primarily by moderating the mosfet switching speed - dV/dt and dI/dt. Faster switching is required for higher efficiency but that comes with increasing EMI/EMC. My question is what is a reasonable target for switching speed for a non-specialist designer? TI's Powerstage Designer does not help because it is easy to choose values that give loss losses eg. the sub 5ns switching speed in my example, but unreasonably fast for a non-hero designer to achieve. Funnily enough I've just watched a video "Impact of MOSFET Gate Resistor on the EMI & Noise Spectrum of a Switch Mode Power Supply". Here: the presenter th-cam.com/video/_r0xtaYMjYQ/w-d-xo.htmlsi=1rDE9wBNhhhj8dzx demonstrates that a 30ns rise time is unreasonably fast from an EMC/EMI viewpoint; 100ns would be much better but probably unacceptable on efficiency grounds and that 50ns is a good compromise. (This was a flyback design, voltages unknown but givem the LISN presumably mains input). [PS] Just noticed the 30ns rise time is actually the 20Vpp gate rise time; we aren't shown the drain voltage fall time but I expect it will be similar. That sounds like a good guideline but I expect the 'reasonable' switching times heavily depends on the power levels and voltages involved for a given architecture. My interest is currently in circa 30W 24V to 12V buck regulation so maybe 50ns is a reasonable target? I appreciate that good layout is likely very important for any design above a watt or two, not that you'd know that looking at some of the cheap Chinese designs...
This is a great tool they should have open sourced it. There are some really good features they could have added like generating an LT spice model and plugins for conversion to digital domain loops. Another good tool to look at is Biricha WDS but ain't free.
Great video; thanks for pointing out a useful tool. An issue that I have with such tools/spreadsheets is they don't provide any guidance to inexperienced designers as to realistic values for the input parameters. Most notably they typically seem to indicate that very low switching losses can be achieved as a result of unrealistically high switching rise and fall times. Eg. I tried the tool for a 18V to 12V/8A synchronous buck at 100kHz with a 33uH inductor and a CSD17579Q5A for the switch FET. I chose 5.8ohms for the total driver resistance (1 ohm driver, 1.8ohm FET Rg + 3ohms gate resistance) and it calculated a mere 82mW switching loss due to switch rise and fall times of 7ns and 6ns. Ok, 5.8 ohms is rather low but I'd expect that achieving such speeds would be *very* optimistic due principally to stray inductance, especially the FET's source inductance. My gut feeling is that 25ns is an ambitous but achievable target but I don't have any real experience to back that up.
I know you've done videos on MOSFET switching but it would be great if you could cover the topic in a bit more detail including what are realistic switching speeds that can be achieved without heroic design and layout skills and EMI considerations. I've done a fair bit of searching but found very little hard information; plenty of videos showing the switching scope traces, but either they use very slow switching times (probably because capturing fast transistions requires expensive scopes and probes) or the timebase is too slow to make any reasonable estimates of the rise/fall times.
You could also cover the benefits/tradeoffs to paralleling smaller switch FETs, rather than using a single larger device, to reduce the dI/dt rates of each FET and thus reducing the effects of stray inductances.
Also it would be helpful if you could suggest typical MOSFET stray inductance values for common packages as they are rarely specified in the datasheets.
[Edit] Finally, to what extent are the speed, and thus efficiency benefits of GAN FETs the result of the very low inductances of their special packages rather than their lower gate charge?
Quite a complex question, but I will try to somehow answer, at least partly - you can get a first idea of a transistors switching speed from the datasheet - usually it has some sort of values given that where practically measured using the test fixture - for the CSD17579Q5A you get 1n/7n fall/rise. Anyway, at 100KHz I would expect switching losses to be small, so the ~82mW value does not seem all that absurd. At this switching frequency, the biggest losses will be conduction. Anyway, you might find a transistor spice model and just create a basic simulation to get a better estimate, even if that will not split the losses into switching and conduction. Regarding package/trace inductance, a rule of thumb is 1nH/mm, its not perfect but its a start. However, at 100KHz, package parasitics are usually not specified since these are not the main contributor - layout and interconnections will be providing most of the issues.
@FesZElectronics Much appreciate your response. Power stage designer defines tr and tf to include the time when the FET d-s current is transitioning *plus* the Vds rise/fall times (ie. when losses occur). Following your suggestion I tried LTSpice using a BSG0811ND (very similar switching specs to the CDS part). The switching loss was 48mW with tr/tf = 4.7ns/5.5ns. These closely matched PSD's calculated 5.5ns/4.7ns. Trise and tfall were 2.8/3.0ns
However adding 3nH parasitic FET source pin inductance quadroupled the sw loss to 195mW with tr/tf = 15.5/16ns. Rise and fall times were little changed to 3.7/2.9ns. I can't remember where I read the 3nH value for a D-PAK.
I'm not sure how easy it would be to limit the stray inductance to even 3nH in a real implementation, hence my question as to how realistic tools like PSD are when it comes to switching speed - in the tool you can increase the driver voltage and reduce the driver resistance to 0 to suggest arbitrarily fast switching speed but in reality I assume limits arise due to the FET's dV/dt and dI/dt limits, EMC considerations and especially the stray inductances; I have no real world experience and am wary of simulations limitations hence my question. The problem with so many educational papers/blogs/videos is they teach the principles but rarely provide real world 'reasonable' numbers.
Also note the TI FET D/S specs are for an impractical 0 ohm driver. I'm not sure how they could have tested that!
As someone that just completed an LLC design based on an ST Micro reference design, I feel your pain. Without going into details, I can say generally what you are asking is about the “magic” of pcb layout. These fine details are kind of an engineering IP of the designer if you will. I suggest you get the basic reference pcb design (buy the kit) and study the layers in detail. Expect several rev level changes as your board evolves. Or pay to have the layout done by a competent designer which has vast experience in your target end device. These guys are not just graphics people. Many are EEs. Just because they have done smps, this is no longer enough experience. They need to know your target chip.
Should you decide to go on your own, the Altium videos on TH-cam regarding smps layout are invaluable. If you go this path, only use a target device which has a reference design offering. Most of the newer devices are basically a micro controller not a power management chip.
Mixed signals of low amplitude (600mv)combined with high dv/dt (400vdc) are a special trick. When in one 16 lead soic. Pfc and half bridge in one device.
@@frnkbooth6871 Thanks for your helpful insights. My view is that designing a state of the art efficiency hard switching converter likely requires super-hero design skills, tools, long experience and cutting edge devices.
However I'm sure that most competent engineers could design a switching regulator with moderate efficiency and with help even get it through EMI/EMC certification - primarily by moderating the mosfet switching speed - dV/dt and dI/dt. Faster switching is required for higher efficiency but that comes with increasing EMI/EMC.
My question is what is a reasonable target for switching speed for a non-specialist designer? TI's Powerstage Designer does not help because it is easy to choose values that give loss losses eg. the sub 5ns switching speed in my example, but unreasonably fast for a non-hero designer to achieve.
Funnily enough I've just watched a video "Impact of MOSFET Gate Resistor on the EMI & Noise Spectrum of a Switch Mode Power Supply". Here: the presenter th-cam.com/video/_r0xtaYMjYQ/w-d-xo.htmlsi=1rDE9wBNhhhj8dzx demonstrates that a 30ns rise time is unreasonably fast from an EMC/EMI viewpoint; 100ns would be much better but probably unacceptable on efficiency grounds and that 50ns is a good compromise. (This was a flyback design, voltages unknown but givem the LISN presumably mains input).
[PS] Just noticed the 30ns rise time is actually the 20Vpp gate rise time; we aren't shown the drain voltage fall time but I expect it will be similar.
That sounds like a good guideline but I expect the 'reasonable' switching times heavily depends on the power levels and voltages involved for a given architecture. My interest is currently in circa 30W 24V to 12V buck regulation so maybe 50ns is a reasonable target? I appreciate that good layout is likely very important for any design above a watt or two, not that you'd know that looking at some of the cheap Chinese designs...
Yep! Nice tool but that's why design verification is soooo important. Thanks for the content!
Very useful tool, thanks.
This is a great tool they should have open sourced it. There are some really good features they could have added like generating an LT spice model and plugins for conversion to digital domain loops. Another good tool to look at is Biricha WDS but ain't free.
I recently played with it a bit. Sadly sometimes it behaves unexpectedly and the documentation is scarce.
Very useful information. Again thanks for the video.
Is there any tool like this for transformer and inductor design ?
Not that I currently know of, but if I find something interesting I will probably review it at some point