Nice video. Thank you. Since the multiplier is a 25 x 18 multiplier, how would a 32x32 or 64x64 bit multiplication be accomplished? I assume it would use multiple blocks.. I envision using these blocks to hardware assist a microprocessor, for instance, and it may be a 32-bit or even a 64-bit processor....
You use multiple blocks to compute partial products. So a 32x32 multiply would use 4 DSP blocks. The 32-bit operands are broken down into a 17-bit and a 15-bit operand. So A*B becomes AH*BH + AH*BL + AL*BH + AL*BL, each of which fitting within the 25x18-bit multiplier. The DSP blocks also contain fast fabric interconnects for such operations, which allow adjacent DSP blocks to connect together (without using LUTs), as well as a 17-bit input shift option from this fast path (since it's a 25x18 multiplier). To do 64-bit multiplication, you need more partial products and more stages (there's a table somewhere, but I can't recall where. In the worst case). It's going to be 16 blocks, since 64-bits can be broken up into 4x 32-bit partial products. However, since the DSP blocks are 25x18 and not 18x18, I think it practically becomes something like 10 blocks for 64-bits.
7 years later, and still useful!
Thanks much for the introduction to Xilinx DSP.
Straight to the point, and really helpful
thank you!
Expanding my knowledge of Vivado software Thank you for sharing
Great video, this helped a lot. Thank you very much!!!
holly fuck this is gold! thanks so much for sharing!
Very straight forward and helpful. Thanks!!
Thank you for video.
Why in addition we need only 17 LUTs?
what does a 25x18 multiplier mean?
when is FPGA preferred over DSP for music?
Thanks!
Nice video. Thank you. Since the multiplier is a 25 x 18 multiplier, how would a 32x32 or 64x64 bit multiplication be accomplished? I assume it would use multiple blocks..
I envision using these blocks to hardware assist a microprocessor, for instance, and it may be a 32-bit or even a 64-bit processor....
You use multiple blocks to compute partial products. So a 32x32 multiply would use 4 DSP blocks. The 32-bit operands are broken down into a 17-bit and a 15-bit operand. So A*B becomes AH*BH + AH*BL + AL*BH + AL*BL, each of which fitting within the 25x18-bit multiplier. The DSP blocks also contain fast fabric interconnects for such operations, which allow adjacent DSP blocks to connect together (without using LUTs), as well as a 17-bit input shift option from this fast path (since it's a 25x18 multiplier). To do 64-bit multiplication, you need more partial products and more stages (there's a table somewhere, but I can't recall where. In the worst case). It's going to be 16 blocks, since 64-bits can be broken up into 4x 32-bit partial products. However, since the DSP blocks are 25x18 and not 18x18, I think it practically becomes something like 10 blocks for 64-bits.
Can FPGA make a multiplication?
Yes fpga can do that. Many fpgas have a dedicated multiplier
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