Oh, on my z80 playground I have most of the z80 lines coming out to a 36 way header along the front of the board. I don't have clk on there though, so I soldered a wire directly to that pin of the z80. It wasn't difficult and did no damage.
A good video for beginners but there are a few anomalies. Your oscilloscope capture shows poor signal integrity from your PCB and Power distribution design. There's so many unneeded artefacts such as ripple on your signals. You're also probably not probing the signals correctly. Your PCB is working in spite of your design (a very common phenomena). I'm guessing you've incorrectly captioned the Z80 control signals (e.g. /M1, /MREQ, /RD, /WR, /RFSH) in you video sans the necessary negation (i.e. '/' or '-' or '*' prefix). Your capture of the /MREQ and /WR signals @3:57 seems incorrect because the /WR signal is asserted whilst /MREQ is negated. The signal timing is fully illustrated in the Z80 data sheets. Your design has the Static RAM access logic correct with using the /MREQ for the static RAM /CS chip select signal. However what many naively do is assume that /MREQ & /WR to indicates a memory write cycle and use it to drive their memory's /CS signal with ((/MREQ & /RD) & (/MREQ & /WR)) This is incorrect, wasteful and a gotcha for newbies particularly back in the mid 1970's where fast memory was very expensive. If you carefully compare the the assertion timing between a memory read and memory write cycle the assertion of /WR signal relative to the /RD is delayed by over 1/2 a clock cycle so the beginning of a memory write cycle is at the assertion of /MREQ with /RD remaining negated. It is designed this way to match the timing for the memory devices of that era. Thus a memory read or write cycle is determined by /MREQ & RFSH (i.e. /RFSH remains negated) and a memory refresh cycle is /MREQ & /RFSH.
And now for Part 3, please! ;)
Nice work. Next up /IOREQ and /INT ?
Exactly that, plus bus request and acknowledge
How do you connect your scope probes to the lines? I'm struggling to connect them to the (socketed) IC on my single board computer.
Oh, on my z80 playground I have most of the z80 lines coming out to a 36 way header along the front of the board. I don't have clk on there though, so I soldered a wire directly to that pin of the z80. It wasn't difficult and did no damage.
@@CircuitBreaker256 Thanks!
I remember being told that division uses more clock cycles than multiplication. Just wondering if your application would show that.
Well there is no z80 instruction for division or multiplication so it would depend on the routines you wrote.
@@CircuitBreaker256 it was the Timex Sinclair. My dad had a switch in it to run European and American programs.
A good video for beginners but there are a few anomalies.
Your oscilloscope capture shows poor signal integrity from your PCB and Power distribution design. There's so many unneeded artefacts such as ripple on your signals.
You're also probably not probing the signals correctly. Your PCB is working in spite of your design (a very common phenomena).
I'm guessing you've incorrectly captioned the Z80 control signals (e.g. /M1, /MREQ, /RD, /WR, /RFSH) in you video sans the necessary negation (i.e. '/' or '-' or '*' prefix).
Your capture of the /MREQ and /WR signals @3:57 seems incorrect because the /WR signal is asserted whilst /MREQ is negated.
The signal timing is fully illustrated in the Z80 data sheets.
Your design has the Static RAM access logic correct with using the /MREQ for the static RAM /CS chip select signal.
However what many naively do is assume that /MREQ & /WR to indicates a memory write cycle and use it to drive their memory's /CS signal with ((/MREQ & /RD) & (/MREQ & /WR))
This is incorrect, wasteful and a gotcha for newbies particularly back in the mid 1970's where fast memory was very expensive.
If you carefully compare the the assertion timing between a memory read and memory write cycle the assertion of /WR signal relative to the /RD is delayed by over 1/2 a clock cycle so the beginning of a memory write cycle is at the assertion of /MREQ with /RD remaining negated. It is designed this way to match the timing for the memory devices of that era.
Thus a memory read or write cycle is determined by /MREQ & RFSH (i.e. /RFSH remains negated) and a memory refresh cycle is /MREQ & /RFSH.
That’s interesting, I’ll have to look into that.