Professor Ben-Yaakov, thank you for an extremely informative presentation. This is one of the most helpful and useful videos. We are very appreciative of the time and effort you put into attempting to improving our understanding of power electronics. Again, thank you. Happy New Year.
Now I understand why secondary capacitor is needed. Your explanation is really to the pin point. Thank you for all your effort you're putting into to enhance our understanding. Wish you a very Happy New Year.
Professor Ben-Yaakov. I also look to you to keep trying to obtain a deeper understanding about SMPS designs. Thanks again for another wonderful video. Happy New year. I visited Tel-Aviv in '07 and '08 and loved the entire experience.
Thank you professor, I never thought this gets that ugly on the secondary side, with second diode not conducting at all. IMO the proper-proper solution would be a current mode push-pull controller - it ensures flux balance from the start, but hey, a few caps work as well!
Thanks for the input. IMO peak current mode will NOT help. It will just make it worse. Look at the secondary current waveform. For PCM you need a triangular waveform and the peak at the required transition point, i.e. large inductor.
Professor, something feels off about the explanation of necessity of that secondary cap, let me try to explain. The assertion is that the DC component through the secondary winding (whatever the cause, it happens to be the duty cycle error here), can cause saturation of the core. The problem with that is that the total current in a transformers' winding is not what causes core saturation, but rather the magnetizing current. The magnetizing current is purely a function of the volt-seconds on a winding (in this case the secondary), so as long as the volt-second balance is maintained on that winding (and it should be with the series cap in primary), the magnetizing current will have an average of zero, while the actual total secondary winding current itself may have a DC component. I'm not sure if my explanation is easy to follow, but I would like to see the integrated measurement of the secondary voltage average and see if the average is zero. If it is, I assert that the magnetizing current is zero, even if the total winding output is not. Maybe it could help to instead use the Lm + ideal transformer model instead of the coupled inductor model to see it here. -Ivan
I did the LTSpice simulation as well, and can see that my assertion is incorrect, and there is still a DC component through the actual magnetizing inductance, but I don't intuitively understand why that is, when the secondary volt-seconds should be zero (they are close, but not zero).
Take one step back. Assume a transformer fed by an AC voltage sources imposing a balanced volt-seconds. Now connect a half wave rectifier (one diode ) on the secondary. It will cause a DC current to flow at the secondary. DC currents in transformers are not necessarily linked to unbalanced volt-second.
It seems to me that adding the two suggested capacitors would be beneficial, even when the circuit is driven directly from mains, without a special driver to increase the frequency above 50/60HZ. Your thoughts?
SPICE requires galvanic path to ground of all parts. For convenience I have connected the "grounds". As you will see there is no problem to disconnect the two parts in reality.
The issue is not BW but phase shift that complicates the compensator (feedback).The closed loop BW will determine the response to input voltage and load steps. In practical systems, a closed loop BW of 1- 4KHz is possible with switching frequency of about 10kHz
What about introducing a dead time in the driver? The duty cycle will be less than 50% but it will be easier to preserve the symmetry. What about intoducing a small gap in the transformer to keep it accomodate some DC? I suppose the same phenomenon occurs when driving the primary in push pull with a center tap instead of in H bridge configuration, correct? Thank you very much for your explanation.
Great presentation as always :-) However, I do not think you are right. The MAX13256 as you mention has a duty cycle of 49% to 51%, but that is likely just for production test. The device has internal flipflop, so the duty will be very close to 50%, except for asymmetry in rise/fall times and propagation delays. Additionally it has internal deadtime. In your simulation you do not model the RDSon of the high and low side FETs. If more current runs in one FET, the RDSon balances out the delivered average to the transformer, and also the RDSon increases with temperature, counteracting the asymmetry. You mention aging of the driver. I do not believe that has any effect. The flipflop does not change with aging and transistor rise/fall times does not either. So all in all, in a practical circuit with non-ideal components this will not be an issue and there is no reason to add a capacitor.
Hi Klaus, I don't agree that the duty cycle of the the MAX13256 can be assumed to be exactly 50%. Rise and fall times, dead time and jitter of the input clock may cause a deviation in the duty cycle and they are all temp dependent. But the primary reason for not assuming 50% is that I am not for trying to outsmart the manufacturer. If he says 49-51% then, in my opinion and experience, it is bad practice and in fact dangerous to assume that you know better. There is also a legal issue here in case of a damaging malfunction. And... it seems that Analog Devices agrees with me. On an advanced unit MAX22256 they show a cap at the primary. If the duty cycle deviation is 1% a cap at the secondary is probably not a must. But I am afraid that you missed the point, which is: no need for this fancy IC. A dual inverting gate driver package connected as an RC oscillator (or plus a 555) is sufficient if you put the two caps.
What about the effects of dead time for the main switcher IC? In the case where there is dead-time and some freewheeling body diodes to perform the conducting, the problem of duty cycle at least on the primary side should be mitigated i would think... Like if you had 1% dead time (1% of the switching period) then you should be able to accommodate for that same amount of deviation from 50%?
@@VEC7ORlt what I mean is during that deadtime the voltage will self-actuate. So if you have it ON for 49% of the time and OFF for 49% of the time, with 2% dead time, then the voltage will self actuate at 50%, without the need for perfectly accurate on and off times. You could also have it ON for 49.2% and OFF for 48.8% or something, I think the "slop" will allow the voltage to self-actuate at 50% still. Not 100% sure tho
I find this a little bit baffling. The asymmetry is caused solely by the driving side. Surely the driving IC is designed to drive the transformer symmetrically. So why then would it have a specification tolerance large enough to cause problems of this sort? That would go against the logic of having an IC (rather than a custom circuit solution) in the first place. This analysis might be useful for linear PSUs too. I understand that the AC mains waveform is rarely distorted in a symmetrical fashion but I admit I do not know whether that distortion means its duty cycle changes from 50% over any period of time. How does one calculate the capacitor size though? Surely that would depend on the leakage inductance and the transformer inductance but in what way?
To be fair, in many low power applications the common designer will not be aware on this fine detail, since a transformer can tolerate some DC current.
Something I did not see mentioned is that driving the primary single-ended means pushing voltage (and eventually current) during the positive excursion but when the drive goes to zero, it is not pushed (or pulled) to zero, it merely falls to zero, how quickly it falls to zero depends upon the impedance of the source. If the drive goes to high impedance then the voltage collapses quickly and you get a spike on the secondary and it won't be symmetrical since this spike only happens on the fall of the primary. An obvious solution is to have push-pull on primary so the drive current is the same in positive and negative halves. This is shown at the end of the video where the positive and negative excursions have MOSFET drivers.
@@sambenyaakov The datasheet says it is intended for up to 10W PSUs and a maximum 300mA current. So you are right in that respect. Then again, I am not sure how beefy a 10W transformer would need to be to tolerate upwards of 100mA DC. In the MAX22256 datasheet, which is a similar IC, a DC blocking capacitor is shown on the primary side in the example application circuit. I think that IC is intended for up to 15W.
Adding capacitors is not feasible for higher power outputs. A better way is to make the drive symmetrical by using a flipflop divider. The only asymmetry is then turn on vs turn off delay of the switches in the primary. Also a better wound transformer should not have more than 0.1% leakage. I have made pushpull converters delivering several hundred watts using this method. One issue is the diode recovery of the output for higher voltage, which can today be solved using SiC diodes.
Thanks Professor, it is always to habe so much fun to wacth your video!
🙏🙂
Professor Ben-Yaakov, thank you for an extremely informative presentation. This is one of the most helpful and useful videos. We are very appreciative of the time and effort you put into attempting to improving our understanding of power electronics. Again, thank you. Happy New Year.
Thanks for the warm words, Comments like yours keep me going.
Now I understand why secondary capacitor is needed. Your explanation is really to the pin point. Thank you for all your effort you're putting into to enhance our understanding. Wish you a very Happy New Year.
👍🙏
So many answered questions! Thank you professor!
👍🙏
Professor Ben-Yaakov. I also look to you to keep trying to obtain a deeper understanding about SMPS designs. Thanks again for another wonderful video. Happy New year. I visited Tel-Aviv in '07 and '08 and loved the entire experience.
Thanks. Come again.
Happy new year professor!
Very interesting video. I hope to keep learning from you in 2023.
Happy new year! Let's continue the knowledge journey😊
great presentation
🙏👍😊
Thank you professor!
👍🙏😊
Great and informative presentation 🙏
👍🙏
Excellent and useful = thank you.
Thanks
Most interesting , thank you .
🙏
Thank you professor, I never thought this gets that ugly on the secondary side, with second diode not conducting at all.
IMO the proper-proper solution would be a current mode push-pull controller - it ensures flux balance from the start, but hey, a few caps work as well!
Thanks for the input. IMO peak current mode will NOT help. It will just make it worse. Look at the secondary current waveform. For PCM you need a triangular waveform and the peak at the required transition point, i.e. large inductor.
@@sambenyaakov As is no - it doesn't even have an output inductor.
Buck cascaded with push-pull is viable solution though.
@@VEC7ORlt Buck? The whole point of this simple converter that it does not require an inductor
@@sambenyaakov For simple solution nothing beats 2 caps. I was just thinking aloud.
@@VEC7ORlt 👍
Professor, something feels off about the explanation of necessity of that secondary cap, let me try to explain. The assertion is that the DC component through the secondary winding (whatever the cause, it happens to be the duty cycle error here), can cause saturation of the core. The problem with that is that the total current in a transformers' winding is not what causes core saturation, but rather the magnetizing current. The magnetizing current is purely a function of the volt-seconds on a winding (in this case the secondary), so as long as the volt-second balance is maintained on that winding (and it should be with the series cap in primary), the magnetizing current will have an average of zero, while the actual total secondary winding current itself may have a DC component.
I'm not sure if my explanation is easy to follow, but I would like to see the integrated measurement of the secondary voltage average and see if the average is zero. If it is, I assert that the magnetizing current is zero, even if the total winding output is not. Maybe it could help to instead use the Lm + ideal transformer model instead of the coupled inductor model to see it here. -Ivan
I did the LTSpice simulation as well, and can see that my assertion is incorrect, and there is still a DC component through the actual magnetizing inductance, but I don't intuitively understand why that is, when the secondary volt-seconds should be zero (they are close, but not zero).
Take one step back. Assume a transformer fed by an AC voltage sources imposing a balanced volt-seconds. Now connect a half wave rectifier (one diode ) on the secondary. It will cause a DC current to flow at the secondary. DC currents in transformers are not necessarily linked to unbalanced volt-second.
It seems to me that adding the two suggested capacitors would be beneficial, even when the circuit is driven directly from mains, without a special driver to increase the frequency above 50/60HZ. Your thoughts?
Low frequency means bulky transformers, generally not favored in modern design.
According to what I see is that this is not an Isolated DC-DC converter since the schematic diagram shows both sides shares the same ground.
SPICE requires galvanic path to ground of all parts. For convenience I have connected the "grounds". As you will see there is no problem to disconnect the two parts in reality.
👍🙏❤
👍🙏😊
Hi professor..
What should be the min bandwidth of open loop system in flyback converter.
Please detail about its pros and cons..
The issue is not BW but phase shift that complicates the compensator (feedback).The closed loop BW will determine the response to input voltage and load steps. In practical systems, a closed loop BW of 1- 4KHz is possible with switching frequency of about 10kHz
What about introducing a dead time in the driver? The duty cycle will be less than 50% but it will be easier to preserve the symmetry. What about intoducing a small gap in the transformer to keep it accomodate some DC?
I suppose the same phenomenon occurs when driving the primary in push pull with a center tap instead of in H bridge configuration, correct?
Thank you very much for your explanation.
Why modify the transformer when you can just add some caps?
Yes, its exactly the same problem.
Great presentation as always :-) However, I do not think you are right. The MAX13256 as you mention has a duty cycle of 49% to 51%, but that is likely just for production test. The device has internal flipflop, so the duty will be very close to 50%, except for asymmetry in rise/fall times and propagation delays. Additionally it has internal deadtime. In your simulation you do not model the RDSon of the high and low side FETs. If more current runs in one FET, the RDSon balances out the delivered average to the transformer, and also the RDSon increases with temperature, counteracting the asymmetry. You mention aging of the driver. I do not believe that has any effect. The flipflop does not change with aging and transistor rise/fall times does not either. So all in all, in a practical circuit with non-ideal components this will not be an issue and there is no reason to add a capacitor.
Hi Klaus, I don't agree that the duty cycle of the the MAX13256 can be assumed to be exactly 50%. Rise and fall times, dead time and jitter of the input clock may cause a deviation in the duty cycle and they are all temp dependent. But the primary reason for not assuming 50% is that I am not for trying to outsmart the manufacturer. If he says 49-51% then, in my opinion and experience, it is bad practice and in fact dangerous to assume that you know better. There is also a legal issue here in case of a damaging malfunction. And... it seems that Analog Devices agrees with me. On an advanced unit MAX22256 they show a cap at the primary. If the duty cycle deviation is 1% a cap at the secondary is probably not a must. But I am afraid that you missed the point, which is: no need for this fancy IC. A dual inverting gate driver package connected as an RC oscillator (or plus a 555) is sufficient if you put the two caps.
What about the effects of dead time for the main switcher IC? In the case where there is dead-time and some freewheeling body diodes to perform the conducting, the problem of duty cycle at least on the primary side should be mitigated i would think... Like if you had 1% dead time (1% of the switching period) then you should be able to accommodate for that same amount of deviation from 50%?
Dead time solves cross conduction problems, not volt-second imbalance.
@@VEC7ORlt what I mean is during that deadtime the voltage will self-actuate. So if you have it ON for 49% of the time and OFF for 49% of the time, with 2% dead time, then the voltage will self actuate at 50%, without the need for perfectly accurate on and off times. You could also have it ON for 49.2% and OFF for 48.8% or something, I think the "slop" will allow the voltage to self-actuate at 50% still. Not 100% sure tho
@@power-max Realistically, are those 2% enough? Diodes will need to conduct, bleed off the DC, reverse recover, all of that in those 2%.
I find this a little bit baffling. The asymmetry is caused solely by the driving side. Surely the driving IC is designed to drive the transformer symmetrically. So why then would it have a specification tolerance large enough to cause problems of this sort? That would go against the logic of having an IC (rather than a custom circuit solution) in the first place.
This analysis might be useful for linear PSUs too. I understand that the AC mains waveform is rarely distorted in a symmetrical fashion but I admit I do not know whether that distortion means its duty cycle changes from 50% over any period of time. How does one calculate the capacitor size though? Surely that would depend on the leakage inductance and the transformer inductance but in what way?
To be fair, in many low power applications the common designer will not be aware on this fine detail, since a transformer can tolerate some DC current.
Something I did not see mentioned is that driving the primary single-ended means pushing voltage (and eventually current) during the positive excursion but when the drive goes to zero, it is not pushed (or pulled) to zero, it merely falls to zero, how quickly it falls to zero depends upon the impedance of the source. If the drive goes to high impedance then the voltage collapses quickly and you get a spike on the secondary and it won't be symmetrical since this spike only happens on the fall of the primary.
An obvious solution is to have push-pull on primary so the drive current is the same in positive and negative halves. This is shown at the end of the video where the positive and negative excursions have MOSFET drivers.
@@thomasmaughan4798the datasheet does show a push-pull drive arrangement on the output of the IC.
@@sambenyaakov The datasheet says it is intended for up to 10W PSUs and a maximum 300mA current. So you are right in that respect. Then again, I am not sure how beefy a 10W transformer would need to be to tolerate upwards of 100mA DC.
In the MAX22256 datasheet, which is a similar IC, a DC blocking capacitor is shown on the primary side in the example application circuit. I think that IC is intended for up to 15W.
Adding capacitors is not feasible for higher power outputs.
A better way is to make the drive symmetrical by using a flipflop divider.
The only asymmetry is then turn on vs turn off delay of the switches in the primary.
Also a better wound transformer should not have more than 0.1% leakage.
I have made pushpull converters delivering several hundred watts using this method.
One issue is the diode recovery of the output for higher voltage, which can today be solved using SiC diodes.
Thanks for sharing. This video deals with low power auxiliary power supply solution.