Fantastic,thank you, I am testing this circuit on my laboratory ups with 8 batteries and it works great! I used to get unbalanced damaged batteries often in the ups system.
Is there a simple circuit that is used to bias the N MOSFET. I know bootstrapping needs to be used, but that requires a pwm. Can you show how to turn-on the MOSFETs in the series strings? I am trying an active balancing using boost buck topology but I can’t keep the MOSFET ON since the boostrap capacitor discharges too fast.
I see two weak points. 1. An MCU needs to feed MOSFETS with different frequencies (to keep a current constant, as I understood you well), and that makes a big problem if cells 1 - 2, and 2 - 3 have different disbalance (because they share switches and capacitors). 2. If we will have cell voltages as 3.5, 3.2, 3.2, 3.5, then that "no need to balance" part will fail, and w ill stop a balancing, and such voltages remain. For me the best balancers are: a DC/AC multi-coil transformer (simple schematic, cheap components, no need to have an MCU, because a balancing happens automatically for all cells at once, moderate balance currents with diodes, or with sync rectifiers, this is possible to use one secondary coil for two cells and a full-bridge topology), then a DC/DC charge pump (moderate balance current, minimal number of switches as Ncell+4, no transformer, needs to measure voltages) and two charge sources (one of them is floating, with a bypassing the most charged cell with charging cells before it and after it, the highest balance current up to 1C, a balancing during a charging, a balancing phase is integrated into a charging one, but needs 2*Ncell 1C switches, and needs to measure voltages)
Sorry to bother you but i tried to recreate the circuit in LTSpice but i cnt get the nMOS driver to work . I tried to use a half bridge driver and a 100k and a 7v Zenner diode like in the picture at 7:30 , in another video you demonstrate a diver that used a few more components , Is this that driver but simplified so it fits on the screen ?
Thank you for sharing your fascinating idea. The given circuit definitly reduces the balancing time compared to the conventional switching capacitor method. Which is a very good performance. Here is a question for the frequency part. I think that a switching capacitor method adopts a fixed duty ratio (0.5 not considering the dead time) with low frequency and usually lean on the cell performance for automatic balacning. However, if the switching frequency is set to be high to reduce the balancing time, won't be the loss caused by the passive components (Cap & Resistor) and Active components will out surpass the advantage? thank you.
Dear Professor, Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype. Hope you will soon upload a video... Best Regards
Was this simulated in LTspice or another program? Also to represent the cells what did you use? I tried with a large capacitor with a reasonable ESR but i am not sure how large should i set them, to be ? 1F 100F ? more less?
So this entire array would need only one half bridge driver , if I understand well . Is there any concern with all that current spreading to all the FETs , so they turn slow. Also what would be an appropriate size for the caps? I assume they are large electrical or tantalum so like 470u or larger? When it comes to that low side sense resistor, the output from the op am was also negative so the op am needs a negative rail and that is not nice but I assume the peacks are more or less identical so I think only the high side of the peacks is enough for it to work, is that correct? Also ,tho this may be a bit out of place, is there a place where you upload these simulations?
Hi Sir could you please make a video on 3 phase active PFC circuit using LTspice... mainly for less than 1KW design what sort of PFC topologies would be preferred ?
Thank you for the video, it is informative and straightforward, as always. The idea is elegant and implementation seems simple. I have one doubt regarding the approach to recognition of the stack of cells being fully balanced. Let's assume we have 4 cells: the upper one is the cell 1, then cell 2, cell 3 and cell 4 connected to the ground. If the cell 1 and cell 4 are having the same voltage, so do cell 2 and cell 3, however cell 1 (or 4) and cell 2 (or 3) voltages differ, then by comparing voltage of cells: 1+2+3 with cells 2+3+4 we obtain the info that all stack is balanced, which is not true. Am I correct, or did I miss something? Regards!
The auxiliary path balances cells 1 and 4. It does not sense 2 and 4. But, deviation of 2 and 4 will quickly spread to 1 and 4, so (as said in the video) there is a need to wait.
Dear Professor, Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype. Hope you will soon upload a video... Best Regards
Fantastic,thank you, I am testing this circuit on my laboratory ups with 8 batteries and it works great!
I used to get unbalanced damaged batteries often in the ups system.
Great. Thanks for sharing
Very interesting. I had a similar idea but never got to fully develop it some time ago. Thank you ever so much.
Great minds think a like😊
A very elegant design! Thanks for sharing.
Thanks
Is there a simple circuit that is used to bias the N MOSFET. I know bootstrapping needs to be used, but that requires a pwm. Can you show how to turn-on the MOSFETs in the series strings? I am trying an active balancing using boost buck topology but I can’t keep the MOSFET ON since the boostrap capacitor discharges too fast.
Have you watched this? th-cam.com/video/MiiMun66f78/w-d-xo.html
@sambenyaakov thank you so much
I see two weak points. 1. An MCU needs to feed MOSFETS with different frequencies (to keep a current constant, as I understood you well), and that makes a big problem if cells 1 - 2, and 2 - 3 have different disbalance (because they share switches and capacitors). 2. If we will have cell voltages as 3.5, 3.2, 3.2, 3.5, then that "no need to balance" part will fail, and w ill stop a balancing, and such voltages remain.
For me the best balancers are:
a DC/AC multi-coil transformer (simple schematic, cheap components, no need to have an MCU, because a balancing happens automatically for all cells at once, moderate balance currents with diodes, or with sync rectifiers, this is possible to use one secondary coil for two cells and a full-bridge topology),
then a DC/DC charge pump (moderate balance current, minimal number of switches as Ncell+4, no transformer, needs to measure voltages)
and two charge sources (one of them is floating, with a bypassing the most charged cell with charging cells before it and after it, the highest balance current up to 1C, a balancing during a charging, a balancing phase is integrated into a charging one, but needs 2*Ncell 1C switches, and needs to measure voltages)
Thanks for comment.
Sorry to bother you but i tried to recreate the circuit in LTSpice but i cnt get the nMOS driver to work . I tried to use a half bridge driver and a 100k and a 7v Zenner diode like in the picture at 7:30 , in another video you demonstrate a diver that used a few more components , Is this that driver but simplified so it fits on the screen ?
Which other video, please?
Thank you for sharing your fascinating idea. The given circuit definitly reduces the balancing time compared to the conventional switching capacitor method. Which is a very good performance. Here is a question for the frequency part. I think that a switching capacitor method adopts a fixed duty ratio (0.5 not considering the dead time) with low frequency and usually lean on the cell performance for automatic balacning. However, if the switching frequency is set to be high to reduce the balancing time, won't be the loss caused by the passive components (Cap & Resistor) and Active components will out surpass the advantage? thank you.
As briefly explained in the video resistance does no affect the efficiency. Switching losses may. See www.ee.bgu.ac.il/~pel/pdf-files/conf156.pdf
Dear Professor,
Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype.
Hope you will soon upload a video...
Best Regards
Will try. Thanks for comment.
@@sambenyaakov dear professor I am very grateful for your response
@@sambenyaakov and desperately looking for the explanatory video ...
Regards
Was this simulated in LTspice or another program?
Also to represent the cells what did you use? I tried with a large capacitor with a reasonable ESR but i am not sure how large should i set them, to be ? 1F 100F ? more less?
For the long runs simulation was by PSIM. Use simulation (LTspice is OK) for selecting components values.
So this entire array would need only one half bridge driver , if I understand well . Is there any concern with all that current spreading to all the FETs , so they turn slow.
Also what would be an appropriate size for the caps? I assume they are large electrical or tantalum so like 470u or larger?
When it comes to that low side sense resistor, the output from the op am was also negative so the op am needs a negative rail and that is not nice but I assume the peacks are more or less identical so I think only the high side of the peacks is enough for it to work, is that correct?
Also ,tho this may be a bit out of place, is there a place where you upload these simulations?
1.For C use Re=1/(fsw C)
2. You can use a an OpAmp based rectifier
3. Sorry
Hi Sir could you please make a video on 3 phase active PFC circuit using LTspice... mainly for less than 1KW design what sort of PFC topologies would be preferred ?
Will try
Thank you for the video, it is informative and straightforward, as always. The idea is elegant and implementation seems simple. I have one doubt regarding the approach to recognition of the stack of cells being fully balanced. Let's assume we have 4 cells: the upper one is the cell 1, then cell 2, cell 3 and cell 4 connected to the ground. If the cell 1 and cell 4 are having the same voltage, so do cell 2 and cell 3, however cell 1 (or 4) and cell 2 (or 3) voltages differ, then by comparing voltage of cells: 1+2+3 with cells 2+3+4 we obtain the info that all stack is balanced, which is not true. Am I correct, or did I miss something? Regards!
The auxiliary path balances cells 1 and 4. It does not sense 2 and 4. But, deviation of 2 and 4 will quickly spread to 1 and 4, so (as said in the video) there is a need to wait.
👍🙏❤️
Thanks
Genial!!!
🙏🙂
Dear Professor,
Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype.
Hope you will soon upload a video...
Best Regards