It still blows my mind that we're in the billions of transistors on CPUs now, basically every single one has to work or the whole chip is useless, and these things run for *decades*. I don't know of any other thing we make as a species that's good for quadrillions of operations with zero maintenance.
Just keep in mind that these situations are being designed by individuals and then being taken and tweaked for scalability by others. Cooperation is the real magic of Engineering.
@@Teth47 I would imagine, that with that scale of transistors, and to have a faulty one kill a whole chip, they will build a few redundancies in, so that if a portion of the chip has a fault, they can just fuse it out, and have a backup circuit take up the slack. At least, that's how I would do it, if designing something with that number of potential failure points. I'd build redundancies in so chips could be "saved" even if one critical part had a fault, and a have a fuse map to choose which parts to enable/disable. Sure, it's eats up some silicon space, but if you has even just 1% used for backup circuits, and it could rescue otherwise failed/faulty chips, I think it would be worth it.
4:46 - I worked at IBM a few years ago (IBM Software Lab). And I remember quite distinctly that we were strongly encouraged to come up with patent applications for the company. Anything was fine as long as it was patentable. We were rewarded with a salary bonus for a successful patent application.
Lithography. You "print" with an acid resistant and removable material, give it a dunk in acid then remove the printed material. There are more complicated processes. The mechanical tolerances of the "printer" determine how small you can print. The failure rate multiplied by the die size will determine the yield rate because of the two dimensional nature.
There's some promising developments in increasing the length they can grow carbon nanotubes, but we still have a long way to go before we're consistently growing nanotubes of indefinite length.
Moore's law was never about this industry jargon of 7nm and 2nm. Those are not the defining limits to how many transistors can be put put on 1000mm square integrated circuit. We could very well have another 12000 times increase in the number of transistors on chips and that is without the actual chip getting larger. So we may have another 12 to 16 doublings ahead of us in terms of how many transistors can be crammed on to a chip. So your Nanotube revolution maybe at some stage play a part.
Glad to have discovered a channel that actually gets the current state of processors and goes into as much detail as possible. Great and well researched content!
Thanks for explaining the disconnection from different companies "nanometers" and the real physical dimensions. I think this is what a lot of people don't understand.
I don't think that removing one bottleneck solve the scaling issue though. The resolution of the lithography process might be high enough to keep increasing the transistor density, but does that mean that it's practical to do so? As far as I understand the real issue might not be Moore's law, but Dennard scaling. If the power density gets to a point where we can't find ways to practically cool a silicon die, we're just hitting a different bottleneck instead.
It's a bit unexpected to see die shrinking is still in full speed Thanks for your informative video and hope we can keep getting higher computation performance! Everyone loves a cute potato, munching wafers and naturally your channel!
What I think will happen in 2024: a world war has been started due to the global chip shortage, even an old 8085 is worth more than a life, and Intel is still stuck on 14 nm
@@TechTechPotato Ah yes. A reason that violent terrorism achieves its aims. I had a google apparently the BBC refused to air it till 2007. I am sure I watched it in like 2003 and thought it was a silly comment.
This crisis is just before overshooting. Time is very near when low power controllers are going to be cheaper than you could imagine. Over productions and many more fabs will make things easier for makers world.
It's nice to know not only what Intel/TSMC/AMD does, but also what is actually researched, great video. Here are my 2 cents for the algorithm, this channel needs to grow.
This goes beyond professionalism. This man and his team IS a full professional institution on these topics. This is how informative channels should be.
By chance this video was suggested, and as a former semi worker my mind is officially blown. At RCA Findlay (later Harris) we advanced to 0.5 um using i-line Canon FPA 1500 steppers back in the early 1990s; that was a big advance from the MPA-501 that were only 1.5 um line width. Thanks for this video.
This is extremely good news, it's getting exponentially harder to scale down even further as we are reaching quantum limits for electrons. The distances between certain features within the transistors can be measured in atoms... (I think IBM made a video/animation using 8 or so atoms in a stickman configuration) Even assuming you could get over the quantum tunneling effects, we cant build circuits smaller than the size of an atom, we would need a breakthrough in optical or full quantum computing. Truly amazing, the cutting edge of applied physics.
Hey TechTechPotatoe. Just found your channel and finding all this in depth CPU talk great. I actually have been meaning to find a channel or a resource that talks about this specifically. Thank you for covering it. I also think it is so cool how you have been invited to places like IBM :). Keep up the great work from another techie that has big aspirations as well.
You really have most intriguing content. I saw you in the "Moore's Law is Dead" episode first - I loved this episode, so I also followed you on your channel.
Most that claim it is dead do not even know what it means and they some how think it has to do with with industry jargon that is being used such as 7nm and 2nm. Do you remember when frequency used to be the big thing in industry.
@@SurelyYewJest My guess is that they will probably take him to a conference room where they have everything they want him to record ready to present and then provide him with pre-recorded videos of the other areas of the lab that has been approved for release.
Just discovered your channel, great video! I'm a PhD MatSci student working on alternate interconnect metals and it's nice to have something somewhat relevant to watch while I'm in lab :)
Ian, small remark, the Wilton facility does not build EUV machines. It produces parts for the ASML Scanner like reticle stages and certain clamping mechanisms. The full EUV machines (Scanner + EUV light source) are build in Veldhoven the Netherlands. ASML San Diego (formerly Cymer) builds big part of the EUV light source. So if you really want to see some EUV technology you need to go to San Diego, not Wilton. Just mentioning it to prevent disappointment.
@@TechTechPotato Yes of parts (related to the Scanner) that end up into the full EUV machine, but they don't do actual work on the 'full' EUV light source. But still a super opportunity to visit that site!.
@@TechTechPotato All EUV used in the U.S are made in the U.S. That was the agreement in the first place. The EUV itself is an American technology. www.eetimes.com/u-s-gives-ok-to-asml-on-euv-effort/
@@someone5582 Not really a surprise a 22 year old article (containing multiple errors btw) does not reflect the current reality. The story might state the intentions that they had at that time, but reality turned out differently. To give you an idea, there was not just 1 EUV light source under development, but at least 3. In the end it was a close race between Cymer and Gigaphoton who would make the first technically and commercially viable light source. Eventually ASML went all in on Cymer, who was developing the light source the article is probably referring to. As development went way to slow, ASML bought Cymer in 2013 and moved a lot of the research facilities (including most of the software development needed) to the Netherlands. Only the last couple of years things are moving back to ASML San Diego (formerly Cymer) again. As a result you will find many parts of the light source being designed, developed and produced in the Netherlands and some neighboring countries. E.g the modular vessel, the vacuum enclosure, where all the magic happens is build in the Netherlands by VDL , the huge laser that fires on these tiny Tin droplets is made by TRUMPF Germany, and all optical mirrors to focus and transport the light beam are created by Zeiss Germany. Intellectual property matters are not really my field of expertise, but I think it's safe to say a statement like 'EUV is American technology' (or any other country for that matter) is wrong on multiple levels. As mentioned multiple parties were trying to develop an EUV light source, the American variant as mentioned in the article is one of them, but other prototypes were developed outside of the US. The owner of the technology is the one holding it's intellectual property / patents. And after Cymer was bought by ASML these EUV patents came in the hand of ASML, look up patent US7453077B2 (EUV light source) if you want. You will see the Current Assignee is ASML Netherlands BV. And yes agreements where made during this acquisition of Cymer by ASML. As the US government considered the technology sensitive for national security ASML is by agreement not allowed to export these EUV light sources to certain listed countries/regimes without permission from the US. The whole political story is way more complicated then this (as ASML is in fact only depends on a GO for delivery from the Dutch government and not from the US one), but it will give you an idea of what is going on. Also be clear the article and myself are only talking about the EUV light source. A working machine consists of a scanner with a light source attached. You need both. As the US has no say in the scanner part and non-EUV lightsources, DUV machines (scanners with a different, slightly older technology light source) are (still) sold to China.
Wonderful content, man. Super informative. Love both the cursory introduction to some technical info as well as the deeper look into history, design, and marketing. Not a careless word thrown in! You do a great job and gained a new subscriber!
Be sure to see CREE/Wolfspeeds new 200mm SiC fab when you are in New York. I would love to hear your thoughts on SiC for high voltage power management.
I worked for Altera for 6 years, long before they became Intel FPGA, and the nm 'measurements' bandied around were largely dictated by the marketing departments even then. Getting an apples to apples comparison between manufacturers was tricky then, probably exponentially harder now.
Sounds like we are getting close to measuring process nodes in picometers. At that point Ian's new tag line could be, "I have pica for picometers" ... Sounds like it should be on a cereal box.
No not really the smallest a transistor can get is around 0.8 nm between source and drain which are 3 silicon atoms in a row and this is without doting the material
A silicon atom is 0.21nm, and you need a few of them, due to doping with other atoms to create the PNP setup needed for a transistor to work. But they are building in 3d and only measure the horizontal plane. So maybe towers of 0.21nm wide could be the most dense they can get.
So you know the foot/meter conversion ratio but you don't know the thumbnail/mm² one? I thought doctors were supposed to be smart. For real though, love your content.
Perfect analysis of cpu manufacturing competitions n company must think about low density transistors n low electricity consumption for low carbon emissions of OUR world n thx for quality vdo🙏🇮🇳🙏💐❤️
Glad you put this out. I retired from the semiconductor industry in 2005. At that time it was obvious we had gone as far as we could with conventional photo printing and quantum effects were impacting transistor design for lower power circuits. Your description of the meaning of X nm's helped me understand the pivot that technology has taken since my retirement.
I'm reminded of an old Get Smart episode where an explanation was being given to Max. After it was done, Max said, "One thing I didn't get." "What's that, Max?" "The part after, it's simple."
Keep in mind that the minimum feature size (2nm) is *much* smaller than the actual transistors. At 333M transistors per square mm, the transistor average spacing is 55nm. That is about 260 silicon atom diameters, while 2nm is only 9.5 atomic diameters.
@@TechTechPotato Yes, I just wanted the viewers to realize how misleading the names are. The chart of transistor densities that you showed, does convey the inconsistencies between manufacturers, but not the magnitude of the difference between feature and transistor size. If you read through comments here and elsewhere, you find that many people still think the names are the transistor sizes.
Judging by your comment, it appeared as if you hadn't watched the video. Which is what a lot of people making those sorts of comments you're referring to end up doing as well.
We need more technical content like this from people with technical degrees. I'm not saying degrees are everything, but when you spend years of your life learning about math and science in a formal setting it gives you a perspective that is uncommon among people who lack a formal education. Lots of stuff on the internet about tech but few really have the knowledge to describe the details accurately. Ian is one of the few.
Man these node shrinks are making me super optimistic for the future. Just imagine, how dense quad patterned GAAFETs would be. Coupled with die stacking and fluid micro channels to increase density on thermally dense regions. We've got many years to look forward to.
The Cat Tax was actually quite reasonable, until I saw the slippers! EEK Get yourself some Uggboots, man! Loved the video. Although I do software architecture, not chip architecture, I still found this fascinating. Thanks.
Thanks for breaking the big numbers down for us. But the B&W pic at 2:09 is actually my root canal picture! Oh - and that black cat is bad luck - might wanna trade it in for a white one. lol And I was just imagining you taking the black cat w/ you on a tour of an IBM transistor clean room facility at 4:32 where they wear those white suits - and it jumping from your arms - you'd never catch it before a 100 million cat hairs came loose!
Very nice video, thnx for posting. However, at ASML Wilton they only make the Top Module for EUV, consisting of the Reticle Handler and Reticle Stage. If you really want to see the complete build of an EUV system, you have to visit ASML in Veldhoven, The Netherlands. And beyond multiple patterning on an EUV system is of course the introduction of the High NA (0.55) EUV system. I agree with you that we will see some interesting shrink in the near future.
I'm very much a layman and it took half the video to figure out it isnt in production. It would have been nice to have mentioned that at the beginning that this was still some way to go before seeing production/ useage. Thumbs up anyway for interesting content.
I can’t even wrap my head around 2nm lithography, but I suspect it’s some trick where it’s really 5-7nm but some crazy stacking it offset gimmick but we will find out eventually. Even 5nm doesn’t make sense to me.
Ever since 14nm and the first finfets, the naming hasn't matched any real physical dimension because the transistor went 3d. This naming is meant to imply a theoretical 2d transistor of that size. At 2nm we move beyond finfets to nanosheets and there are multiple generations of that to come
Our fab is also working on a 2nm node length too. One of the chief issues we are facing at this length are quantum mechanical properties, as the electron crosses over the threshold only to become a positron and no longer an electron.
Underrated content man. That clip at the end is fascinating too. But I also want my own wafer... Cant decide which one to order on Ebay lol. I wonder if itll go good with creme...
Thank you for providing this amazing channel. Only "criticism" or request rather - is keeping the illustration photos+graphics on screen a bit longer - they flash by way too fast to ponder and try to remember or think about them and their implications. :) again Thanks a lot - immediate subscribe :D All the best from Oslo, Norway :)
I have question: Do computers that are intending to go into space, done with chips that are on a much larger nanometer scale to account for cosmic rays?
And my favorite CPU was the Motorola 68000, invented first for military use in the mid 1970s, which animated the first 16 bit the personal computers in the mid 80s and many 16 bit consoles of the early 90s only had 68000 transistors on this large rectangular CPU.
11:27 80^2/8^2=100 „Was that a big news in the newspapers? That EUV-machines is enabling a 100x shrink of transistors? That was the fine print under „Moore’s Law is dead! -Right??“ 13:25 - lol - this is the first video I watched on this channel / that got recommended to me, and I truly had no idea that Moore’sLaw wasn’t dead... - thanks a lot!
The issue that occurs every day (every second, really) is neutron radiation that upsets logic states and causes soft errors. And yes, it does get worse as devices are scaled down.
I think the only measurement that should be used to describe process technology generation is transistors per quare millimeter because that's the only metric that cannot be twisted by the marketing department. Even there you should also include the frequency you can run those transistors.
@@TechTechPotato If you want accurate results, you could specify one exact transistor type for that metric. I think that even if the metric used *any type* the results would be much better than current "nm" names. Another option is just to forget about the process level comparisions and just get chip manufacturers to tell the total transistor count for a chip in addition to chip area and we could just compute average transistors per square millimeter over the whole chip. That would better reflect the fact that the process technology is not the only thing that matters for actual performance and that chips are not just transistors only.
actually, the nanometer parameter in node is referring to the *GATE LENGTH* , the part of the transistor that links source and drain terminals and this gate is only one piece in the transistor design. If the process is 7nm then the minimum gate length the fab is offering is 7nm. But there are other parameters that each fab has which also affects the transistor size and the quality of the trnasistor, so this is why the densities are different from fab to fab. But if the node size is 7nm, the gate length will always be 7nm at all the fabs. Therefore the saying of wikichip "different fabs have different counting metodologies" is incorrect
When you said about 333 million transitors per mm square that honestly broke my brain. Utterly astonishing engineering going on.
It still blows my mind that we're in the billions of transistors on CPUs now, basically every single one has to work or the whole chip is useless, and these things run for *decades*. I don't know of any other thing we make as a species that's good for quadrillions of operations with zero maintenance.
That's also peak.
Intel's 14nm wasn't twice as dense as TSMC's 14nm at the end of the day. If it was there's no way Ryzen would have been competitive.
Just keep in mind that these situations are being designed by individuals and then being taken and tweaked for scalability by others. Cooperation is the real magic of Engineering.
Just don't try to count them by hand.
@@Teth47 I would imagine, that with that scale of transistors, and to have a faulty one kill a whole chip, they will build a few redundancies in, so that if a portion of the chip has a fault, they can just fuse it out, and have a backup circuit take up the slack. At least, that's how I would do it, if designing something with that number of potential failure points. I'd build redundancies in so chips could be "saved" even if one critical part had a fault, and a have a fuse map to choose which parts to enable/disable. Sure, it's eats up some silicon space, but if you has even just 1% used for backup circuits, and it could rescue otherwise failed/faulty chips, I think it would be worth it.
4:46 - I worked at IBM a few years ago (IBM Software Lab). And I remember quite distinctly that we were strongly encouraged to come up with patent applications for the company. Anything was fine as long as it was patentable. We were rewarded with a salary bonus for a successful patent application.
Sounds like they were getting over on you and all there employees 😂😂😂
@@stephenmontez6754 patents were properly filled with all the inventors listed
I love these videos where you explain the details of how the industry and manufacturing process works. Ive learned a lot from watching your videos
Lithography. You "print" with an acid resistant and removable material, give it a dunk in acid then remove the printed material. There are more complicated processes. The mechanical tolerances of the "printer" determine how small you can print. The failure rate multiplied by the die size will determine the yield rate because of the two dimensional nature.
hey Shank, a small world! We caught you there 😜
Same here. Thanks !
@Kenn Honson X .
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Wiiu portable running off a watch battery is now possible
I'm still waiting for that carbon nanotube revolution ¯\_(ツ)_/¯
graphene turns out to be hard to make at scale.
Yassss
There's some promising developments in increasing the length they can grow carbon nanotubes, but we still have a long way to go before we're consistently growing nanotubes of indefinite length.
Won't happen without a process scaling like lithography did.
Moore's law was never about this industry jargon of 7nm and 2nm. Those are not the defining limits to how many transistors can be put put on 1000mm square integrated circuit.
We could very well have another 12000 times increase in the number of transistors on chips and that is without the actual chip getting larger.
So we may have another 12 to 16 doublings ahead of us in terms of how many transistors can be crammed on to a chip.
So your Nanotube revolution maybe at some stage play a part.
Glad to have discovered a channel that actually gets the current state of processors and goes into as much detail as possible. Great and well researched content!
Thanks for explaining the disconnection from different companies "nanometers" and the real physical dimensions. I think this is what a lot of people don't understand.
Agree, I always assumed it was directly proportional to density.
Jim Keller always floors me with how he can talk about such high-minded concepts like they are simple and elegant. I also paid the cat tax.
I mean - regarding this - his comic sans represents the ultimate swag
What is cat tax
But Moore’s Law is still dead as an economic law
@@BirdTho Video chapter dedicated to his cat. Pay the tax or cat will bite you.
Except he kept calling a cross an 'x'.
The content on this channel is so consistently high-quality that I am upgrading from Bulldozer to Nehalem
Really really appreciate that you've got links to everything. What most informative channels should do
ddr 6 oh common it will be ddr 7 lol
its useless links but ..
Some other wouldn't even give source. I flag them as misinformation
@@Mr11ESSE111 don't say that the person put effort on it you'll make the person sad :'(
@@thefirstsin efforts for useless links again
Never watched your channel before, it just showed up on my feed and I had to give you some kudos on the title.
that Jim Keller clip really puts things into perspective.
I don't think that removing one bottleneck solve the scaling issue though. The resolution of the lithography process might be high enough to keep increasing the transistor density, but does that mean that it's practical to do so? As far as I understand the real issue might not be Moore's law, but Dennard scaling. If the power density gets to a point where we can't find ways to practically cool a silicon die, we're just hitting a different bottleneck instead.
@@cosmiczeppelin there's always new challenges to overcome, but the important bit is that there's no fundamental limit that we're hitting yet.
@@cosmiczeppelin we can always run the coolant through the chip itself. Packaging might get a bit complicated though
It was explained very well. Guess I learned some stuff.
@@Greitone oh jesus christ, i rue the day that microfluidics enter the semiconductor scene for... cooling...
This channel is amazing, you’re talking about all the interesting things I’m into and I can’t find other places
It's a bit unexpected to see die shrinking is still in full speed
Thanks for your informative video and hope we can keep getting higher computation performance!
Everyone loves a cute potato, munching wafers and naturally your channel!
What I think will happen in 2024: a world war has been started due to the global chip shortage, even an old 8085 is worth more than a life, and Intel is still stuck on 14 nm
Star Trek predicted an Irish Reunification in 2024.
Nah by then Intel's 2 new Arizona fabs will be in play.
I for one will be eating sand in hopes of shitting out a video card.
@@TechTechPotato Ah yes. A reason that violent terrorism achieves its aims. I had a google apparently the BBC refused to air it till 2007. I am sure I watched it in like 2003 and thought it was a silly comment.
This crisis is just before overshooting. Time is very near when low power controllers are going to be cheaper than you could imagine. Over productions and many more fabs will make things easier for makers world.
I think that video had exactly the right amount of detail for me. All the visual explanation really helped that a lot
It's nice to know not only what Intel/TSMC/AMD does, but also what is actually researched, great video. Here are my 2 cents for the algorithm, this channel needs to grow.
This goes beyond professionalism.
This man and his team IS a full professional institution on these topics. This is how informative channels should be.
High-quality content on Tech Tech Potato. I went into the description to find Jim Keller's video and it was actually cited properly!
By chance this video was suggested, and as a former semi worker my mind is officially blown. At RCA Findlay (later Harris) we advanced to 0.5 um using i-line Canon FPA 1500 steppers back in the early 1990s; that was a big advance from the MPA-501 that were only 1.5 um line width. Thanks for this video.
This is extremely good news, it's getting exponentially harder to scale down even further as we are reaching quantum limits for electrons. The distances between certain features within the transistors can be measured in atoms... (I think IBM made a video/animation using 8 or so atoms in a stickman configuration)
Even assuming you could get over the quantum tunneling effects, we cant build circuits smaller than the size of an atom, we would need a breakthrough in optical or full quantum computing. Truly amazing, the cutting edge of applied physics.
Hey TechTechPotatoe. Just found your channel and finding all this in depth CPU talk great. I actually have been meaning to find a channel or a resource that talks about this specifically. Thank you for covering it. I also think it is so cool how you have been invited to places like IBM :). Keep up the great work from another techie that has big aspirations as well.
You really have most intriguing content. I saw you in the "Moore's Law is Dead" episode first - I loved this episode, so I also followed you on your channel.
Do you have a link
Most that claim it is dead do not even know what it means and they some how think it has to do with with industry jargon that is being used such as 7nm and 2nm.
Do you remember when frequency used to be the big thing in industry.
This just came up in recommended, man I'm glad it did. You've got some brilliant content.
I feel like this content is filling a Coreteks/Adored hole, a potato size hole.
Notice outro sounds has that Coretex vibe. Am expecting a groveling voice and none comes
I miss Jim from adoredtv.
@@mrrolandlawrence Jim is now freethinker, he debunks conspiracy theories, it's really amusing.
much better than Coreteks IMHO
Interestingly, "patata" which literally means potato in Spanish is also used as slang for heart. "Me llegó a la patata" = "It reached my heart"
what I think ? I think this Channel Deserve more Love And Attention , Great job keep it going please !
You NEED to go visit all of those fabs ASAP and produce videos, that would be absolute prime content!
HAH, good luck getting cameras in to record much. Even HVM fabs are heavily locked down. Research fabs?
@@SurelyYewJest My guess is that they will probably take him to a conference room where they have everything they want him to record ready to present and then provide him with pre-recorded videos of the other areas of the lab that has been approved for release.
Just discovered your channel, great video! I'm a PhD MatSci student working on alternate interconnect metals and it's nice to have something somewhat relevant to watch while I'm in lab :)
Well, the key question for is "how's the performance?" And a concrete answer to that question doesn't exist yet. But hopefully it will be good.
Ian, small remark, the Wilton facility does not build EUV machines. It produces parts for the ASML Scanner like reticle stages and certain clamping mechanisms. The full EUV machines (Scanner + EUV light source) are build in Veldhoven the Netherlands. ASML San Diego (formerly Cymer) builds big part of the EUV light source. So if you really want to see some EUV technology you need to go to San Diego, not Wilton. Just mentioning it to prevent disappointment.
Huh. Their PR told me the Wilton plant does a lot of EUV assembly.
@@TechTechPotato Yes of parts (related to the Scanner) that end up into the full EUV machine, but they don't do actual work on the 'full' EUV light source. But still a super opportunity to visit that site!.
@@TechTechPotato All EUV used in the U.S are made in the U.S. That was the agreement in the first place. The EUV itself is an American technology.
www.eetimes.com/u-s-gives-ok-to-asml-on-euv-effort/
@@someone5582 Not really a surprise a 22 year old article (containing multiple errors btw) does not reflect the current reality. The story might state the intentions that they had at that time, but reality turned out differently. To give you an idea, there was not just 1 EUV light source under development, but at least 3. In the end it was a close race between Cymer and Gigaphoton who would make the first technically and commercially viable light source.
Eventually ASML went all in on Cymer, who was developing the light source the article is probably referring to. As development went way to slow, ASML bought Cymer in 2013 and moved a lot of the research facilities (including most of the software development needed) to the Netherlands. Only the last couple of years things are moving back to ASML San Diego (formerly Cymer) again. As a result you will find many parts of the light source being designed, developed and produced in the Netherlands and some neighboring countries. E.g the modular vessel, the vacuum enclosure, where all the magic happens is build in the Netherlands by VDL , the huge laser that fires on these tiny Tin droplets is made by TRUMPF Germany, and all optical mirrors to focus and transport the light beam are created by Zeiss Germany.
Intellectual property matters are not really my field of expertise, but I think it's safe to say a statement like 'EUV is American technology' (or any other country for that matter) is wrong on multiple levels. As mentioned multiple parties were trying to develop an EUV light source, the American variant as mentioned in the article is one of them, but other prototypes were developed outside of the US. The owner of the technology is the one holding it's intellectual property / patents. And after Cymer was bought by ASML these EUV patents came in the hand of ASML, look up patent US7453077B2 (EUV light source) if you want. You will see the Current Assignee is ASML Netherlands BV.
And yes agreements where made during this acquisition of Cymer by ASML. As the US government considered the technology sensitive for national security ASML is by agreement not allowed to export these EUV light sources to certain listed countries/regimes without permission from the US. The whole political story is way more complicated then this (as ASML is in fact only depends on a GO for delivery from the Dutch government and not from the US one), but it will give you an idea of what is going on.
Also be clear the article and myself are only talking about the EUV light source. A working machine consists of a scanner with a light source attached. You need both. As the US has no say in the scanner part and non-EUV lightsources, DUV machines (scanners with a different, slightly older technology light source) are (still) sold to China.
Thanks for the content Ian, here's one for the algorithm :D
Wonderful content, man. Super informative. Love both the cursory introduction to some technical info as well as the deeper look into history, design, and marketing. Not a careless word thrown in! You do a great job and gained a new subscriber!
Be sure to see CREE/Wolfspeeds new 200mm SiC fab when you are in New York. I would love to hear your thoughts on SiC for high voltage power management.
The retro style, but REAL old videos inserted in awesome
I worked for Altera for 6 years, long before they became Intel FPGA, and the nm 'measurements' bandied around were largely dictated by the marketing departments even then. Getting an apples to apples comparison between manufacturers was tricky then, probably exponentially harder now.
People have mistaken taken Moore's law to mean the increase in computing speed and other industry jargon.
First video of yours i have seen. Instantly subscribed, fantastic information, equally well explained. Love it!
Sounds like we are getting close to measuring process nodes in picometers. At that point Ian's new tag line could be, "I have pica for picometers" ... Sounds like it should be on a cereal box.
Nah, they will go to angstroms (a tenth of a nm). Plus they will hit the limit soon on size reduction
No not really the smallest a transistor can get is around 0.8 nm between source and drain which are 3 silicon atoms in a row and this is without doting the material
we cant, the atoms are bigger than picometers
There’s actually very little room left at the bottom. Advances are now majority driven by design rather than scaling. Case in point, this IBM design.
A silicon atom is 0.21nm, and you need a few of them, due to doping with other atoms to create the PNP setup needed for a transistor to work.
But they are building in 3d and only measure the horizontal plane. So maybe towers of 0.21nm wide could be the most dense they can get.
Thanks for explaining the very complicated topic in a simple way!
Solid video, great tables and references. Keep up the good work.
> Moore Room
hehe
moore didn't say you couldn't do 2 nm he just said 6 nm was the size of a single silicon atom that's all
Really good video. I wonder what the yields on these things are?
So you know the foot/meter conversion ratio but you don't know the thumbnail/mm² one? I thought doctors were supposed to be smart.
For real though, love your content.
Perfect analysis of cpu manufacturing competitions n company must think about low density transistors n low electricity consumption for low carbon emissions of OUR world n thx for quality vdo🙏🇮🇳🙏💐❤️
I'm here for the cat tbh (love what you're doing with the channel).
Glad you put this out. I retired from the semiconductor industry in 2005. At that time it was obvious we had gone as far as we could with conventional photo printing and quantum effects were impacting transistor design for lower power circuits. Your description of the meaning of X nm's helped me understand the pivot that technology has taken since my retirement.
I love the decriptions below the video. The links, the papers are so informative. Thanks your content its really edu-tainment.
I don't really quite get everything, but i know the algorithm just struck gold recommending this channel.
These videos are much too detailed and in-depth for my interests, but I'm very glad they exist and are of such quality. Rock on
I really appreciate the reference in the title to my boy Richard Feynman! The guy was a genius
@@lordjaashin because he wants?
I'm reminded of an old Get Smart episode where an explanation was being given to Max. After it was done, Max said, "One thing I didn't get." "What's that, Max?" "The part after, it's simple."
I love your channel ... an interview with Jim Keller on this channel will be fabulous
:)
Keep in mind that the minimum feature size (2nm) is *much* smaller than the actual transistors. At 333M transistors per square mm, the transistor average spacing is 55nm. That is about 260 silicon atom diameters, while 2nm is only 9.5 atomic diameters.
Keep in mind one of the first things I mention in the video is that it's only a name.
@@TechTechPotato
Yes, I just wanted the viewers to realize how misleading the names are. The chart of transistor densities that you showed, does convey the inconsistencies between manufacturers, but not the magnitude of the difference between feature and transistor size. If you read through comments here and elsewhere, you find that many people still think the names are the transistor sizes.
Judging by your comment, it appeared as if you hadn't watched the video. Which is what a lot of people making those sorts of comments you're referring to end up doing as well.
@@TechTechPotato
When I find other videos on the topic, I'm recommending to viewers that they go to your channel for better detailed information.
@@TechTechPotatoan engineer should not pick-up Marketing speek too much
Your videos are informative, interesting and easy to listen to. Thanks for the videos!
Came for the tech talk, stayed for the kitty (and those dope slippers!)
So glad I stayed on through to the end to collect on the cat tax.
Love the video, this is very, very interesting.
Indeed! Very useful!
This is my first time watching your channel. Immediately subbed.
We need more technical content like this from people with technical degrees. I'm not saying degrees are everything, but when you spend years of your life learning about math and science in a formal setting it gives you a perspective that is uncommon among people who lack a formal education.
Lots of stuff on the internet about tech but few really have the knowledge to describe the details accurately. Ian is one of the few.
Man these node shrinks are making me super optimistic for the future.
Just imagine, how dense quad patterned GAAFETs would be. Coupled with die stacking and fluid micro channels to increase density on thermally dense regions.
We've got many years to look forward to.
The Cat Tax was actually quite reasonable, until I saw the slippers! EEK Get yourself some Uggboots, man! Loved the video. Although I do software architecture, not chip architecture, I still found this fascinating. Thanks.
I just love this whole channel now, keep sharing knowledge! Please!
just discovered this channel. I’ll pay attention. Subscribed.
Thanks for breaking the big numbers down for us. But the B&W pic at 2:09 is actually my root canal picture! Oh - and that black cat is bad luck - might wanna trade it in for a white one. lol And I was just imagining you taking the black cat w/ you on a tour of an IBM transistor clean room facility at 4:32 where they wear those white suits - and it jumping from your arms - you'd never catch it before a 100 million cat hairs came loose!
Very nice video, thnx for posting. However, at ASML Wilton they only make the Top Module for EUV, consisting of the Reticle Handler and Reticle Stage. If you really want to see the complete build of an EUV system, you have to visit ASML in Veldhoven, The Netherlands. And beyond multiple patterning on an EUV system is of course the introduction of the High NA (0.55) EUV system. I agree with you that we will see some interesting shrink in the near future.
Recently started watching your chanel, i’ve never learned so much about and yet know so little... This is such an interesting topic!
This video in a nutshell: Everything is a lie, and you can't trust anything.
Thank you for saving 15 minutes of my life.
@@J235304204 Still worth watching, I think. It was interesting to get some insider perspective on _why_ it may largely be marketing hype.
I'm very much a layman and it took half the video to figure out it isnt in production. It would have been nice to have mentioned that at the beginning that this was still some way to go before seeing production/ useage. Thumbs up anyway for interesting content.
I love how they used Comic Sans for the presentation
Change title to IBM's New 2nm CPU vs 7nm vs 10nm - Amazing explanation!
I can’t even wrap my head around 2nm lithography, but I suspect it’s some trick where it’s really 5-7nm but some crazy stacking it offset gimmick but we will find out eventually. Even 5nm doesn’t make sense to me.
Ever since 14nm and the first finfets, the naming hasn't matched any real physical dimension because the transistor went 3d. This naming is meant to imply a theoretical 2d transistor of that size. At 2nm we move beyond finfets to nanosheets and there are multiple generations of that to come
Magnificent ! The algorithm provided me with a channel worth instant subbing ! 👍
God I wish I got half as exited about my field as I do when watching you explaining CPU manufacturing
Our fab is also working on a 2nm node length too. One of the chief issues we are facing at this length are quantum mechanical properties, as the electron crosses over the threshold only to become a positron and no longer an electron.
Excellent Video. Thank you for sharing.
Good job conveying actual information
This is really cool and hard to wrap my head around.
The tech has gone so far since the Commadore computer in the 80'S
The ASML office in Wilton doesn’t build the whole EUV systems, only some sub-modules. The complete systems are built in the Netherlands.
This is by far without a doubt my favorite intro ever hahahaha
Underrated content man. That clip at the end is fascinating too. But I also want my own wafer... Cant decide which one to order on Ebay lol. I wonder if itll go good with creme...
IBM were issued 9130 patents last year.
Thank you for providing this amazing channel. Only "criticism" or request rather - is keeping the illustration photos+graphics on screen a bit longer - they flash by way too fast to ponder and try to remember or think about them and their implications. :) again Thanks a lot - immediate subscribe :D All the best from Oslo, Norway :)
I have question: Do computers that are intending to go into space, done with chips that are on a much larger nanometer scale to account for cosmic rays?
I liked the cat part of the video. 😀
"There's plenty Moor Room" - Haha, you just got a new subscriber for that. :p
Every video is a banger. Congrats on the growth bossman.
And my favorite CPU was the Motorola 68000, invented first for military use in the mid 1970s, which animated the first 16 bit the personal computers in the mid 80s and many 16 bit consoles of the early 90s only had 68000 transistors on this large rectangular CPU.
Thanks. It is very informative and explained very well.
Can't wait to try out some 2nm Ryzen or Intel CPU in a few years!
What a new world of semiconductors. When I started in the industry the feature size was 5 micron!
Nice topic! more on this stuff please!
Love the inclusion of the cat tax! :)
11:27 80^2/8^2=100 „Was that a big news in the newspapers? That EUV-machines is enabling a 100x shrink of transistors? That was the fine print under „Moore’s Law is dead! -Right??“ 13:25 - lol - this is the first video I watched on this channel / that got recommended to me, and I truly had no idea that Moore’sLaw wasn’t dead... - thanks a lot!
It would be interesting to know how these FET densities performed during EMP attacks since that is the ultimate consideration in military engineering.
The issue that occurs every day (every second, really) is neutron radiation that upsets logic states and causes soft errors. And yes, it does get worse as devices are scaled down.
funny thing I watched that jim keller video, but I really didn't get what he was talking about 100 %, now I get it. Thanks doctor.
Can’t imagine, I’m currently working on 14nm pathways which blows my mind already
I think the only measurement that should be used to describe process technology generation is transistors per quare millimeter because that's the only metric that cannot be twisted by the marketing department. Even there you should also include the frequency you can run those transistors.
The problem is that it can be manipulated. What types of transistors - simple ones or large flip-flops? What's the right ratio?
@@TechTechPotato If you want accurate results, you could specify one exact transistor type for that metric. I think that even if the metric used *any type* the results would be much better than current "nm" names.
Another option is just to forget about the process level comparisions and just get chip manufacturers to tell the total transistor count for a chip in addition to chip area and we could just compute average transistors per square millimeter over the whole chip. That would better reflect the fact that the process technology is not the only thing that matters for actual performance and that chips are not just transistors only.
Great scoop. Your best video in terms of views so far mate 👍
Sometimes I miss working in Bldg. 323. I've been at Rohnler Acres for 14 years now so I can only imagine how much has changed overall.
Thank you for your work. One day you'll be doing a show on sub-nanometer. Looking forward to it.
actually, the nanometer parameter in node is referring to the *GATE LENGTH* , the part of the transistor that links source and drain terminals and this gate is only one piece in the transistor design. If the process is 7nm then the minimum gate length the fab is offering is 7nm. But there are other parameters that each fab has which also affects the transistor size and the quality of the trnasistor, so this is why the densities are different from fab to fab. But if the node size is 7nm, the gate length will always be 7nm at all the fabs. Therefore the saying of wikichip "different fabs have different counting metodologies" is incorrect
very comprehensive Knowledge video. thank you sir
Great video, very insightful!