5-Stage Pipeline Processor Execution Example (v1.1)

Discusses how a set of instructions would execute through a classic MIPS-like 5-stage pipelined processor. Also looks at calculating the average CPI for the instruction sequence.
NOTE: This example assumes there is NO branch delay slot.

[@wokewook8237]

Cant believe this only came out 4 days ago... helped me so much on a homework assignment thank you

[@fran14cruz]

This! is what I've been looking for like crazy for ages!!!!!!! thank God I found it.
And no, I'm not overdoing it. Thank you very much!

[@aspiringpianist4358]

Isn't it 13 instructions in the loop? (including 5 to 17)....or did he include the 18th cycle?

[@matthewwatkins88]

It does say it takes 13 (17) cycles to complete the loop (so I'm unsure about the issue)

[@aspiringpianist4358]

@@matthewwatkins88 yup just realized...Great work!!

[@jejunegamingtv1359]

With Data Forwarding?

[@matthewwatkins88]

Listed to the video more closely. The word forwarding is mentioned 3 times between 3:00-4:00.

[@Vwcz]

boom roasted

[@LordFers]

But are not 11 instructions? Why you not considered the 11-instruction?

[@matthewwatkins88]

I do consider all of the instructions, but not every case goes through all 11 cases.

[@matthewwatkins88]

I should say all 11 instructions