A Semi-formal approach to coverage analysis and System-on-Chip debugging

A Semi-formal approach to coverage analysis and System-on-Chip debugging
The most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow.