Thankyou for digging into this apparently elegant and very useful circuit over these 2 videos. I use a variation of this as a dual differential transconductance amplifier/IV stage for my audio DAC and although I had the equation for calculating the gain, I never broke it down into small signal analysis. with the right, lowish cap, highish gm fet, biased into class A and driving the gate so-as to present AVCC/2 as a virtual GND at the input for the dac, it makes for a VERY low distortion, if somewhat brute force IV convertor that competes and in many cases betters objective performance you get from all but the best OPA based convertors, with a handful of parts.. When I first built it, it was much earlier in my journey, before I really knew how circuits worked at a small signal level, but the build was capable of better than -123dB THD+N, with a DAC 2 generations ago; which was difficult to even measure with an Audio Precision System 2 back then. I arrived here today as I have been thinking about reworking the IV for the new DAC parts and with a GAN device and wrapping it in a servo loop, so I can DC couple, run a lower voltage, lower dissipation design than the enhancement mode mosfet version. The higher current output of the new dac parts (4x) allow me to drop the size of the power resistors too (I splurged on Vishay foil TO220 $$$ fort a bit of fetishism). The lower voltage required will enable the use of a higher performance VREG; which is a bonus for a stage with such low PSRR. That circuit ran at +/-45VDC, with ~150ma bias, resulting in an IV stage that needs to dissipate nearly 50W (for 2 balanced channels) including the regulated PSU and needs a heatsink almost as big as my amplifier ... lol. with new GAN devices, I can lower the voltage for similar or better performance and use only an aluminium PCB as heatsink and hopefully take less effort in device matching. With the last version I needed to build a test jig to test hundreds of fets to match quads for transconductance at the design's operating point/temp. I just need to choose the right modern SMD device to work in linear operation, without too high a gate charge, when most modern low RDSON SMD fets are designed for hard switching and have large cap. Of course all care will need to be taken in PCB design. I'm Just working out how to tackle the different device character of GAN VGS diode/clamping voltage/behavior and whether that rules them out. I dont think so, as with the common gate construction i'm not feeding the signal to the gate, it is only fed with a DC bias to match the desired virtual ground voltage I want to see at the input node.
@@JordanEdmundsEECS Sir, Currently I am using Chenming Hu's Modern Semiconductor Devices for my studies along with your lectures. But just tell me which source will be good for numericals? Sorry for pestering you too much in your busy schedule.
Hi, Jordan I understand the first KCL but dont really understand the second KCL. 1. The current going to ro should be (GmVgs+ I test). And split into left (to current source) and right path (to Rd) 2. GmVgs in the left path is pointed downward means negative from the perspective of node 2 3. The right path is (-Vout)/Rd, negative since it is leaving node 2 But why i cannot get the same answer as you do? Is there something i did wrong? Thanks
Thankyou for digging into this apparently elegant and very useful circuit over these 2 videos. I use a variation of this as a dual differential transconductance amplifier/IV stage for my audio DAC and although I had the equation for calculating the gain, I never broke it down into small signal analysis. with the right, lowish cap, highish gm fet, biased into class A and driving the gate so-as to present AVCC/2 as a virtual GND at the input for the dac, it makes for a VERY low distortion, if somewhat brute force IV convertor that competes and in many cases betters objective performance you get from all but the best OPA based convertors, with a handful of parts..
When I first built it, it was much earlier in my journey, before I really knew how circuits worked at a small signal level, but the build was capable of better than -123dB THD+N, with a DAC 2 generations ago; which was difficult to even measure with an Audio Precision System 2 back then.
I arrived here today as I have been thinking about reworking the IV for the new DAC parts and with a GAN device and wrapping it in a servo loop, so I can DC couple, run a lower voltage, lower dissipation design than the enhancement mode mosfet version. The higher current output of the new dac parts (4x) allow me to drop the size of the power resistors too (I splurged on Vishay foil TO220 $$$ fort a bit of fetishism). The lower voltage required will enable the use of a higher performance VREG; which is a bonus for a stage with such low PSRR. That circuit ran at +/-45VDC, with ~150ma bias, resulting in an IV stage that needs to dissipate nearly 50W (for 2 balanced channels) including the regulated PSU and needs a heatsink almost as big as my amplifier ... lol.
with new GAN devices, I can lower the voltage for similar or better performance and use only an aluminium PCB as heatsink and hopefully take less effort in device matching. With the last version I needed to build a test jig to test hundreds of fets to match quads for transconductance at the design's operating point/temp. I just need to choose the right modern SMD device to work in linear operation, without too high a gate charge, when most modern low RDSON SMD fets are designed for hard switching and have large cap.
Of course all care will need to be taken in PCB design. I'm Just working out how to tackle the different device character of GAN VGS diode/clamping voltage/behavior and whether that rules them out. I dont think so, as with the common gate construction i'm not feeding the signal to the gate, it is only fed with a DC bias to match the desired virtual ground voltage I want to see at the input node.
Hey Jordan, Can you start a series on current mirrors
Nice explanation. Thank you.
Thank you so much for these videos!
Thank you so much, my exam is in two days and you saved me 😭 thank you sir
Thank you so much!
Welcome!
Thank you Sir
6 unavailable videos are hidden ??? can you please show them It helps me study
Excuse me, could you tell me why you ignore the Rsig? solving in Rout or Rin
same question
Jordan, when will you make videos for BJT Amplifiers too?
Hopefully in the next couple of weeks, but if I forget, feel free to pester me about it xD
@@JordanEdmundsEECSCan you tell me that should I watch your MOSFET videos first or BJT? I mean it is ok to read anything first or is it some priority.
MOSFETs are much easier to analyze because their gate has an infinite input resistance, so I would start with MOSFETs.
@@JordanEdmundsEECS Sir, Currently I am using Chenming Hu's Modern Semiconductor Devices for my studies along with your lectures. But just tell me which source will be good for numericals? Sorry for pestering you too much in your busy schedule.
These are all for low frequency models? Should there not be capacitances everywhere?
Dear god yes there are capacitances everywhere. Inductors too, although they are pretty tiny. And antennas. Yes, these are all low-frequency models.
Hi, Jordan
I understand the first KCL but dont really understand the second KCL.
1. The current going to ro should be (GmVgs+ I test). And split into left (to current source) and right path (to Rd)
2. GmVgs in the left path is pointed downward means negative from the perspective of node 2
3. The right path is (-Vout)/Rd, negative since it is leaving node 2
But why i cannot get the same answer as you do? Is there something i did wrong?
Thanks