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14:04 -> Shouldn't it be? V1= T2*Vref/(RC) = NT*Vref/(RC), then N=(Va*(2^n))/VrefAm I right?In a dual slope adc, the digital data shouldn't depend on the counting period,this is one of its adavantages compared to the single slope adc...
At 18:22 : Shouldn't it be 0-(1/16)Vref instead of 0-(1/2) ?
in dual slope ADC with out using AND gate get we obtain same result or not
$e7
In flash type no of comparator is 2^n-1 but here is 8 how
that is minimum number
nice,,,, its help full...
Very helpfull it was
/snoozefest
14:04 -> Shouldn't it be? V1= T2*Vref/(RC) = NT*Vref/(RC), then N=(Va*(2^n))/Vref
Am I right?
In a dual slope adc, the digital data shouldn't depend on the counting period,this is one of its adavantages compared to the single slope adc...
At 18:22 : Shouldn't it be 0-(1/16)Vref instead of 0-(1/2) ?
in dual slope ADC with out using AND gate get we obtain same result or not
$e7
In flash type no of comparator is 2^n-1 but here is 8 how
that is minimum number
nice,,,, its help full...
Very helpfull it was
/snoozefest