Cache Replacement Policies - RR, FIFO, LIFO, & Optimal

แชร์
ฝัง
  • เผยแพร่เมื่อ 30 ม.ค. 2025

ความคิดเห็น • 18

  • @panchammayank224
    @panchammayank224 3 ปีที่แล้ว +23

    I studied digital electronics from your channel 4 years ago and got good marks in my btech . I could not thanked you at that time. Happy teacher's day sir ❤️

  • @florianmanuelschmid489
    @florianmanuelschmid489 9 หลายเดือนก่อน +2

    amazingly educational: easy to follow, slides carefully crafted, teacher's voice is very dynamic, makes it fun to listen!
    small remark: at 9:06, the 100% should be 100 without the % sign
    despite that, content is 1+ thanks so much!

  • @creedforgreed8080
    @creedforgreed8080 3 ปีที่แล้ว +3

    Cso oh god 💥💥💥💥💥💥
    Bro who ever ece student watches you definitely will subscribe you.
    I'll recommend all ece cs it student or aspirants to it ce to watch your channel.

  • @sandipdas5684
    @sandipdas5684 3 ปีที่แล้ว +5

    I want to know who unliked this video and for what reason? It is such a great lecture... respect to you with lots of love sir...

  • @sffedits
    @sffedits 3 ปีที่แล้ว +3

    Happy teacher's day ❤️

  • @shubhamkhanal2977
    @shubhamkhanal2977 ปีที่แล้ว

    Thank you so much for this informative video
    Really appreciable

  • @nandakumarmunaganti2644
    @nandakumarmunaganti2644 3 ปีที่แล้ว +2

    Please continue ur Aptitude & Reasoning classes & update ur Playlist, coz I think some of the Discrete Maths classes are also part of Aptitude...

  • @Eswar.T-i2d
    @Eswar.T-i2d หลายเดือนก่อน +3

    At 8:50 of time in the Vedio sir told the misses are 7 but he also counted the 7 but it is there in the table could anyone please clarify it

    • @jannegrey
      @jannegrey หลายเดือนก่อน

      I'm not sure what you mean, but let's try: 2,3,4,7,6,3,4,7,5,4,7,8 for fully associative, 4 line cache with FIFO replacement policy. So in order:
      2 - cache miss (compulsory, after that 2 will be in cache, until evicted)
      3 - cache miss (compulsory, after that 3 will be in cache, until evicted)
      4 - cache miss (compulsory, after that 4 will be in cache, until evicted)
      7 - cache miss (compulsory, after that 7 will be in cache, until evicted)
      6 - cache miss (capacity miss, because cache is full, after that 6 will be in cache, until evicted. To place it in cache we evict first block that was written to cache, which is 2)
      3 - cache hit, since it was loaded previously
      4 - cache hit, since it was loaded previously
      7 - cache hit, since it was loaded previously
      5 - cache miss (capacity miss, because cache is full, after that 5 will be in cache, until evicted. To place it in cache we evict first block that was written to cache, which is 3, we evicted 2 earlier)
      4 - cache hit, since it was loaded previously
      7 - cache hit, since it was loaded previously
      8 - cache miss (capacity miss, because cache is full, after that 8 will be in cache, until evicted. To place it in cache we evict first block that was written to cache, which is 4, we evicted 2 and 3 earlier)
      Overall we had 12 blocks requested - 7 of them were misses (4 of them compulsory, because you always take compulsory miss on the first request of the block; 3 of them capacity, because cache was full and blocks had to be evicted in order to make room for new blocks.
      The 7 you see in the table is "Block number 7". The 7 he talks about as cache misses is the amount of times block was requested and was not in cache upon request (had to be fetched).
      Misses here are represented by red arrows above the block numbers. Two 7's you mentioned have nothing to do with each other.
      If you have any further questions - feel free to ask.

  • @santhipriyapriya9828
    @santhipriyapriya9828 3 ปีที่แล้ว +1

    Thank you...

  • @zlatanian7257
    @zlatanian7257 2 ปีที่แล้ว +3

    heeeeeelooo everyone and weeeeeeelcome baaaack

  • @duytran6059
    @duytran6059 ปีที่แล้ว

    can you explain why RR is not implemented in ARM anymore?

  • @yeshesdevi
    @yeshesdevi 3 ปีที่แล้ว

    Is the optimal algorithm totally infeasible? I am thinking it might be possible if we at least assume the future can be predicted from the recent past.
    What comes to mind is that a recurrent random event, such as hitting a memory page or database record, can be modeled as a Poisson distribution. Hence, given its average occurrence over previous time intervals {t_0, t_1, t_2, .... t_n}, we can calculate the probability of it occurring x times over the next interval t_n+1. Then prioritize the blocks (or records) with the highest probability. The one with the lowest probability will be eligible for eviction first.

  • @mokoepa
    @mokoepa 3 ปีที่แล้ว

    I like... 👍🏾

  • @tulikagupta3998
    @tulikagupta3998 3 ปีที่แล้ว

    are you uploding more videos on this playlist??

  • @shubham1581
    @shubham1581 ปีที่แล้ว