Hello sir, This video is great but it will more help full, if you add a practical programming video.... I need help in spi flash programming if you can .....then please .....thank you
Great, very smart, Can you give a clarity on TXE & RXNE in SPI_SR (SPI status register) bit frame. Are they interrupts or empty buffer bits. You said they are interrupts (@6.45 on tape) but based on user manual they are be an empty buffer bits. please could you give clarity on this. thank you in advance.
Can you provide the doc link to for the specifications you are using? I'm writing RTL code for this protocol so required detail description....let me know thanks
As spi protocol does not have any specific bit order (either from msb to lsb or lsb to msb) so how this happened? Is it configurable through spi peripheral register ? Kindly clearify it.
You should not configure like that. Similar to UART baud rate, SPI master and slave should have the same clock frequency because a clock pulse is used to determine a change in data and an event in sampling data either in the transmission or the receiving end. MCU vendors do have delay registers which can be configured in the master node.
Nice video .. can you help me I am working on the stm32f103c8 trying to establish spi master slave communication STM to STM using SPL library issue is that txe flag remain reset .
Hi Mamta, Thanks for the feedback. Assuming there is no hardware problem. During configuration due to some mistakes we face lot of communication issues. Please have a look on below steps: 1. Check for the data sheet and confirm all the req steps are taken care during initialization. 2. Prob CRO to see clock signal is generating properly (req freq) during data transmission. 3. Prob CRO to check MOSI line during transmission.
@@TechVedas thanks actually issue in intializing SPI in stm32f103c8 nothing is being written on SPI2 registers even after intialiazation. Gpio clock is set gpio configred SPI clock SPI2en bit is set Can you please help me ?
Hi mamta, If you have done SPI communication, then please help me to write the code. I am also using the same stm device. So if you can ,please help me.....
I don't why are you explaining same things again and agin in every video. It will be better if you explain the thing that you mention in the name of video and cover picturesl.
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One more great video sir.. Thanks
Thanks for the great comment..
Great video ❤
Hello sir, This video is great but it will more help full, if you add a practical programming video....
I need help in spi flash programming if you can .....then please .....thank you
Extremely well defined!
Thank you, It was really good!
Nice explaination
Great, very smart,
Can you give a clarity on TXE & RXNE in SPI_SR (SPI status register) bit frame. Are they interrupts or empty buffer bits. You said they are interrupts (@6.45 on tape) but based on user manual they are be an empty buffer bits.
please could you give clarity on this.
thank you in advance.
Can you provide the doc link to for the specifications you are using? I'm writing RTL code for this protocol so required detail description....let me know thanks
Nice work bro. Please make videos on Embedded Linux and Raspberry Pi.
As spi protocol does not have any specific bit order (either from msb to lsb or lsb to msb) so how this happened?
Is it configurable through spi peripheral register ?
Kindly clearify it.
Got it
you can configure through LSB FIRST bit in SPI_CR1[7] register.
What is dc chain and one to one ? In spi
spi manual use kar sakte he?
Nice bosss!!!
nice
What will happen if the clock of master is different from the slave?
You should not configure like that. Similar to UART baud rate, SPI master and slave should have the same clock frequency because a clock pulse is used to determine a change in data and an event in sampling data either in the transmission or the receiving end. MCU vendors do have delay registers which can be configured in the master node.
Nice video .. can you help me I am working on the stm32f103c8 trying to establish spi master slave communication STM to STM using SPL library issue is that txe flag remain reset .
Hi Mamta, Thanks for the feedback.
Assuming there is no hardware problem. During configuration due to some mistakes we face lot of communication issues. Please have a look on below steps:
1. Check for the data sheet and confirm all the req steps are taken care during initialization.
2. Prob CRO to see clock signal is generating properly (req freq) during data transmission.
3. Prob CRO to check MOSI line during transmission.
@@TechVedas thanks actually issue in intializing SPI in stm32f103c8 nothing is being written on SPI2 registers even after intialiazation. Gpio clock is set gpio configred SPI clock SPI2en bit is set Can you please help me ?
Hi mamta, If you have done SPI communication, then please help me to write the code. I am also using the same stm device. So if you can ,please help me.....
This guy had explained this cpol and cphase in previous video and now again explaining same thing.
I don't why are you explaining same things again and agin in every video. It will be better if you explain the thing that you mention in the name of video and cover picturesl.
DONT WATCH !! Too many ads
Only Indians understand you. Might as well make this video in hindu.
Not true at all. Very good video, keep up the good work!
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