what a great method of teaching, regret that I did not come across these videos earlier ! Doc, do you have any platform where doubt on Power Electronics can be asked to you directly?
Gareth, that awesome background music is from TrackTribe and is called Drive In. Here's a link for your listening pleasure. th-cam.com/video/HfWjx6VDVJo/w-d-xo.html I'm sorry it hampers your concentration. Power electronics is all about "concentration" of electrical charge and the ability to move lots of that charge quickly. Have a great day and thanks for watching. Make sure to subscribe to the channel.
Hi Daryl, thank you. For the capacitor sizing, start first with the working DC voltage requirements for the output. A capacitor that is rated for 35VDC has a different physical size than a capacitor that is rated for 100VDC. Then look at your switching frequency and output ripple requirements for the rated load. This will determine the amount of capacitance required. If the output load current is high and the ripple values are lower, you will need more capacitance. See the equation in the video with C = Vo*(1-D)/(8*L*deltaVo*f^2). While increasing the switching frequency helps, it comes at the expense of higher switching losses in your MOSFETs. Finally, you will need to decide on the type of capacitor. Your typical options are electrolytic or multi-layered-ceramic-chip (MLCC) styles. Smaller electronics often utilize MLCCs. Sorry, but there's no real good answer for your questions. Design can be messy, but it is always fun. Best wishes on your design. -Dr. K
Often one assumes the load is resistive and because the output voltage is relatively constant ( with the exception of the voltage ripple), the average output current is constant. The output capacitor is therefore used to store and provide charge to help maintain that constant voltage assumption. Thank you for the question and best wishes on your design. -Dr. K
Your equation for I_0 must assume a 50% duty cycle for it to be valid. What is the general expression for I_0 when D != 50%? Or am I in error here? Sorry, not seeing it.
It's independent of the duty cycle. The duty cycle will determine the slope of the current flowing through the inductor. If D is closer to 1, then the slope will be positive with less of a slope as compared to the slope when the capacitor discharge current back to the load over the interval (1-D)Ts. See 9:48 and notice that the capacitor current of discharging to charging at DTs/2 and then peaks in value at DTs. It still charges but at a lower rate until half-way through the (1-D)Ts interval. Therefore, the capacitor is charging during half of the switch period and discharges during the other half of the period. Hope that helps. -Dr. K
Hi Bahadir, for this example I assume positive current is flowing into the capacitor and I am using the passive sign convention for power dissipation of the device. However, at this point in time, the capacitor is providing energy to the connected load and therefore the capacitor is providing charge to the load and the current is exiting the capacitor. The capacitor is sourcing energy. As the current increases through the inductor, it will increase to the point where the capacitor will start to recharge again and the current will be positive (i.e. the capacitor will be sinking power). Hope this helps with the explanation and thanks for watching. -Dr. K
This is awesome. I like the mathematical treatment. Makes one understand and not just use formulae not knowing where they com from. Great!!!
Thank you for the kind words. Glad the videos helped. Best wishes on your designs. -Dr. K
I like the starting music vibe , this is funky electronic science 😅❤️
Thank you.
Just found your channel. I hope to make videos as informative as this some day.
Hi RGB. I just visited your channel. Nice work. Your vids are great quality. Let me know if you ever need some help. -Dr. K
what a great method of teaching, regret that I did not come across these videos earlier ! Doc, do you have any platform where doubt on Power Electronics can be asked to you directly?
Dr, please. I can't concentrate on this video with that awesome country tune in the background. Who is that?
Gareth, that awesome background music is from TrackTribe and is called Drive In. Here's a link for your listening pleasure. th-cam.com/video/HfWjx6VDVJo/w-d-xo.html I'm sorry it hampers your concentration. Power electronics is all about "concentration" of electrical charge and the ability to move lots of that charge quickly. Have a great day and thanks for watching. Make sure to subscribe to the channel.
Good video Doc, what energy capacity properties do we consider when sizing the capacitor for our converter
Hi Daryl, thank you. For the capacitor sizing, start first with the working DC voltage requirements for the output. A capacitor that is rated for 35VDC has a different physical size than a capacitor that is rated for 100VDC. Then look at your switching frequency and output ripple requirements for the rated load. This will determine the amount of capacitance required. If the output load current is high and the ripple values are lower, you will need more capacitance. See the equation in the video with C = Vo*(1-D)/(8*L*deltaVo*f^2). While increasing the switching frequency helps, it comes at the expense of higher switching losses in your MOSFETs. Finally, you will need to decide on the type of capacitor. Your typical options are electrolytic or multi-layered-ceramic-chip (MLCC) styles. Smaller electronics often utilize MLCCs. Sorry, but there's no real good answer for your questions. Design can be messy, but it is always fun. Best wishes on your design. -Dr. K
Thank you so much sir
You are welcome. Best wishes on your designs. -Dr. K
Why can we assume Io is constant while the voltage accross the capacitor is not constant?
Often one assumes the load is resistive and because the output voltage is relatively constant ( with the exception of the voltage ripple), the average output current is constant. The output capacitor is therefore used to store and provide charge to help maintain that constant voltage assumption. Thank you for the question and best wishes on your design. -Dr. K
it depends on the duty cycle D
Your equation for I_0 must assume a 50% duty cycle for it to be valid. What is the general expression for I_0 when D != 50%? Or am I in error here? Sorry, not seeing it.
It's independent of the duty cycle. The duty cycle will determine the slope of the current flowing through the inductor. If D is closer to 1, then the slope will be positive with less of a slope as compared to the slope when the capacitor discharge current back to the load over the interval (1-D)Ts. See 9:48 and notice that the capacitor current of discharging to charging at DTs/2 and then peaks in value at DTs. It still charges but at a lower rate until half-way through the (1-D)Ts interval. Therefore, the capacitor is charging during half of the switch period and discharges during the other half of the period. Hope that helps. -Dr. K
@@powerelectronicswithdr.k1017 Thanks, it makes perfect sense now. Amazing lectures BTW. This coming from a guy with many years as an EE.
@@pb48711 PB, thank you very much. -Dr K
Why does the capacitor current start negative side.
Hi Bahadir, for this example I assume positive current is flowing into the capacitor and I am using the passive sign convention for power dissipation of the device. However, at this point in time, the capacitor is providing energy to the connected load and therefore the capacitor is providing charge to the load and the current is exiting the capacitor. The capacitor is sourcing energy. As the current increases through the inductor, it will increase to the point where the capacitor will start to recharge again and the current will be positive (i.e. the capacitor will be sinking power). Hope this helps with the explanation and thanks for watching. -Dr. K
I would just call it push pull because only push pull can drive two fet at different on time