False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions

[@msubash4053]

Good explanation. I appreciated you. Please do more

[@TeamVLSI]

Thank you, I will

[@venkatavinod2798]

Great explanation. 👍.Very useful ❤️... please upload more 🙏...

[@TeamVLSI]

Thank you Venkata, Sure we will upload more.

[@ArunKumar-wu4px]

Very nice explanation...

[@TeamVLSI]

Thanks Arun.

[@habibakhatunnesaragi6259]

Nice explanation

[@TeamVLSI]

Thanks habiba,
Keep watching.

[@venkatvish9039]

Your videos are great!!!

[@TeamVLSI]

Glad you think so Venkat!

[@msaideroglu]

Very good.

[@TeamVLSI]

Many many thanks @Msaid!

[@akshaynagathan9237]

Thank you sir!!

[@rahulvermarahul8435]

Nice! Please do add videos on Setup and Hold Time violation and how to fix them to take some example

[@TeamVLSI]

Thanks Rahul!
We will try to cover the said topic soon.

[@sane4895]

6:40 sir, if two ff are having diffrent frequency then we can do timing analysis by Multicycle concept right?
If yes then why we need to declar that as false path
If No then what u explained in MCP concept regarding two diffrent frequency

[@TeamVLSI]

Hi,
It all depends on the relation of two clocks, If both are independent then false path can be defined between them.
But suppose if the another clock is just derived from a clock divider or multiplier, in that case we may go for multicycle path requirement.

[@sane4895]

@@TeamVLSI by independent clk means they are coming from diffrent sources or they just have diffrent duty along with diffrent frequency but coming from same source ?

[@TeamVLSI]

@@sane4895 Yes, different sources.

[@sane4895]

@@TeamVLSI thankyou sir fir your quick respons😊

[@arunpandiyananbarasu1455]

Nice video,Explained nicely,More about falsepaths can be found at chapter11:false paths in book "Constraining Designs for Synthesis and Timing analysis"by Sridhar gandadharan,Sanjay churiwala.

[@TeamVLSI]

Thanks Arun. Yes that is a good book.

[@pavan.kumar.muttinenimutti9977]

Explain about path group and how to give weightage to that path

[@TeamVLSI]

Okay Pavan.

[@pavan.kumar.muttinenimutti9977]

Please explain about half cycle path

[@TeamVLSI]

Thanks Pavan, Noted.

[@prasannakulkarni8187]

I feel, it might not be right example. It's logic minimisation.. AB+ B = B. So we don't need OR gate..
Whether Logic synthesiser will not minimise it??

[@that__thing7417]

can anyone brief me about the precedence the tool comsiders. if multicycle path and setmaxlatency are given. what will tool prioritize

[@TeamVLSI]

Tool will try to meet the latency target.

[@coastalfly5508]

What's the difference between False path and disable timing? Please make a video

[@TeamVLSI]

Hi,
Both are different. Will write in our blog soon. Thank you for your suggestion.

[@harshasiriki5704]

Then why false paths are introducing in Design??

[@TeamVLSI]

Hi Harsha,
I explained this point in video.
These path exist but we need to exclude these path in timing analysis.

[@rutwikajmera50]

You write both places ff3 in truth table, kidnly please correct it admin.

[@TeamVLSI]

Thanks Rutwik for catching the mistake. Actually 4th column is FF4/D.
I will try to annotate the correction.

[@rutwikajmera50]

@@TeamVLSI yes sir