32:39 I think this benchmark might be misleading, if there is no dependency chain between the `fdiv d0, d1, d0` and `fmov d0, 2.0`, i.e. if `d0` is not used as an operand between these two instructions (assuming this block executes in a loop), then the full latency of fdiv is not observed. 0.9 ns on an M2 is what, 3 clock cycles?
It’s generally just called A64 assembly. There’s a minor variant Apple made but it’s not very different (it just moves types on SIMD operations from the registers to the instruction mnemonic). The syntax is defined officially by Arm themselves, so there’s no confusion, unlike with x86.
13:05 link to Aarch64 bit patterns. Where does the link point to?
32:39 I think this benchmark might be misleading, if there is no dependency chain between the `fdiv d0, d1, d0` and `fmov d0, 2.0`, i.e. if `d0` is not used as an operand between these two instructions (assuming this block executes in a loop), then the full latency of fdiv is not observed. 0.9 ns on an M2 is what, 3 clock cycles?
Hey can I get the slides or the link to the bit patterns
What’s the syntax of this type of assembly called? Anyone can tell me?😅
I don't think the language has a formal name. I think the syntax is for LLVM's AArch64/ARM64 assembler.
It’s generally just called A64 assembly. There’s a minor variant Apple made but it’s not very different (it just moves types on SIMD operations from the registers to the instruction mnemonic). The syntax is defined officially by Arm themselves, so there’s no confusion, unlike with x86.
This audio clips to zero after each word that is spoken. The result is hard to listen to.