Self-checking testbench in VHDL

The associated blog post:
vhdlwhiz.com/h...
A self-checking testbench is an automatic testbench. It checks the VHDL module, the device under test, without relying on the developer to check that the output is correct. In the end, a “Test: OK”, or “Failed” will be printed out, indicating that the VHDL module is functioning correct or not.
In this video talk about the importance of having a testbench for each and every module in your design. If you have to revisit you VHDL code in the future, it will be difficult to verify the correctness of the module just by looking at the waveform. You may have forgotten the details about the inner workings of the code. Therefore, your should spend at least as much time creating self-checking VHDL testbenches as you spend writing the RTL modules.

[@mohitsrivastav9350]

Hi Jonas. I saw the tutorial videos on basics of VHDL. Do you have couses for professional VHDL coders ? I mean coding practises for high reliability and testability. I am new in this field and i have experienced that rather than spending time on writing test bench.... it is faster to define the code in small modules and then implement them one by one with Integrated Logic analyzer based debugging..... May be i am too confident on my coding but i do want to learn better approaches.... Let me know your thoughts on this..... if you can make a video on this it will be great.... i find many people who take this approach but i am still not sure waht is the correct way...

[@atharvaksh1168]

what are u holding?

[@VHDLwhiz]

That's a breadboard with a Lattice FPGA and a dot matrix LED display mounted on it. It's the prototype that we create in my next VHDL and FPGA course. I talked about it briefly towards the end of this video.