in 56:51 are we assuming 16 banks. each vector is stored in a bank? so each iteration we can parallelly fetch from each bank? Would it be more efficient if we store 16 elements of the vector across all banks. and then each iteration we can process 16 elements of the vector. so in total we can finish the loop in 50/16 * 2 iterations?
48:57 for memory banking, are we assuming data bus size=size of one vector element or size of entire vector? at 48:57, memory access for each vector element take M=10 cycles. and we start accessing an element each cycle. can we just start accessing all N=16 elements at time 0 and we will get all data at time t=10?
Hey, this is a great course, I am watching all of it. I have to 2 questions in this lecture: 1) Isn't vector processing like normal pipepline? 2) Is VLIW in example of MIMD since its doing executing instructions on different (independent) data?
vector processing is implemented using a pipeline; you're not wrong but the conditions under which this particular pipeline is operating are slightly different and enable a lot of things : 1. there can be no dependencies within a vector itself; neither can there be any control flow => we can eliminate all dependency checking & branch prediction logic from hardware 2. we can make very deep pipelines in vector processors because we don't have to deal with branch mis-direction penalties/stalling because of point 1 3. each stage (or unit) of a vector processor is unique and operating on a different data element; the pipelines discussed so far operated on scalar values => the stages defined were completely different
to answer the second question, "single data element" and "multiple data element" is synonymous with "scalar" and "vector", e.g., an integer vs an array
in 56:51 are we assuming 16 banks. each vector is stored in a bank? so each iteration we can parallelly fetch from each bank?
Would it be more efficient if we store 16 elements of the vector across all banks. and then each iteration we can process 16 elements of the vector. so in total we can finish the loop in 50/16 * 2 iterations?
48:57
for memory banking, are we assuming data bus size=size of one vector element or size of entire vector?
at 48:57, memory access for each vector element take M=10 cycles. and we start accessing an element each cycle. can we just start accessing all N=16 elements at time 0 and we will get all data at time t=10?
Hey, this is a great course, I am watching all of it. I have to 2 questions in this lecture:
1) Isn't vector processing like normal pipepline?
2) Is VLIW in example of MIMD since its doing executing instructions on different (independent) data?
vector processing is implemented using a pipeline; you're not wrong but the conditions under which this particular pipeline is operating are slightly different and enable a lot of things :
1. there can be no dependencies within a vector itself; neither can there be any control flow => we can eliminate all dependency checking & branch prediction logic from hardware
2. we can make very deep pipelines in vector processors because we don't have to deal with branch mis-direction penalties/stalling because of point 1
3. each stage (or unit) of a vector processor is unique and operating on a different data element; the pipelines discussed so far operated on scalar values => the stages defined were completely different
to answer the second question, "single data element" and "multiple data element" is synonymous with "scalar" and "vector", e.g., an integer vs an array