I know Im asking randomly but does anyone know of a way to log back into an Instagram account?? I stupidly forgot my account password. I appreciate any tricks you can give me
@Kai Zaid I really appreciate your reply. I found the site thru google and im waiting for the hacking stuff now. Seems to take quite some time so I will get back to you later with my results.
Hai team 1.First of all thanks for the stuff u guys place here. 2.The animated or the images you give for detailed explanation really help a lot in understanding the subject easily. 3.I want you to please update the videos on STA based on the concepts in STA-Bhaskara. From chapter 5 to till end if you take the things placing as different videos for each topic where explaining the topics in easy way would help us a lot. 5.I am also a working Physical design engineer -,ur work and the idea of this channel is great . 6.Want you to wali through the allstages of physical design from synthesis (optional) , floorplan to routing . 7.Anyways some of the signoff checks u already started explaining.Want you to go through some more signoff checks too for to explain them too in further videos . 8.There are some tools too like starrc..primetime ....calibre ..virtuoso or Icc2 among all it would be helpful if you show the execution of starrc .. primetime ..calibre where you shall tell regarding the inputs and process we carryout in tools. 9.If anything needed I can also help ,you can contact me on mail thousif.shaik9@gmail.com or 8179898460. 10.Thanks for your hardwork . From Thousif shaik
Ma'am,in hold analysis we have to consider only the skew in propagated mode,as we r checking in the same/single clock edge,the jitter factor we shall not consider or add on the calculation.
In that reg to reg path we have a common clock buffer so in that case cppr come into picture right.....so in that report.....no cppr value add how it's possible possible?
OCV, Derate and CPPR all are interrelated. To account OCV in the design we give derate..and because buffers in the common clock path will have different derate values because it is common in data as well as clock path, it will add extra pessimism. To remove that extra pessimism we add CPPR. I will soon make a video on this :)
@@backtobasics5602 in that OCV ....we accounting the PVT... variation only. In that cppr we will removing the common clock path buffer delay we make it as zero...why means....in that setup check we take as a RT path is min and AT path is max....so in the common clock path buffers.... not act at same min and max..... that..y we need remove the entire common clock path buffers delay...at zero for that only we introduce the CPPR ....?
Hi in the Set up and Hold Time Vedio you gave 2 inequality equation for Set up and Hold time. My question is how much Positive Slack is required or how much Negative Slack is required to determine Set up and Hold Violation . They can be any number or is that fixed?
Hi ... Please consider if u find it correct for hold we take only noise margin not jitter we don't consider jitter in case of hold because hold check is done at same clock edge for launch and capture.. Thank you
In the last part data arrival time is -0.35 and data required time is 0.17, but you mentioned it as 0.35 - 0.17 = 0.18 ... why is the negative sign ignored?
First check whether the congestion is due to cells or pins . In the tool go for congestion maps and check the histogram . So if the congestion is due to cell density then select the particular cells and then create a placement partial blockage or if it's due to pin density create keep out margin. Later this in the PD tool you can go for reset placement and the do place_opt or refine_opt now if it's more congestion then enable congestion driven placement to active before performing place ,_opt or refine opt Thanks better check websites bro..
@@backtobasics5602 Thankyou for your lectures.. Please do the lectures fastly.. Don't take this much time.. There is 1 month gap between 1 video to another.. Please make video atleast within 15 days...
![[안방1열 풀캠4K] 베이비몬스터 'DRIP' (BABYMONSTER FullCam)│@SBS Inkigayo 241110](http://i.ytimg.com/vi/AQ4RIghEvUs/mqdefault.jpg)
Thanks a lot for all the explanations and clearing concepts in this series.
It is the best video available on this topic. Great job! The explanation is very conducive.
Thanks Aditya :)
Exceelent mam ! One of best video
Good video about timing reports.
hey can you please explain the timing_report generated by tempus for STA.
This is a really good video.
Please add videos on cdc, fixing timing violation and analysing timing paths etc...
Keep the good work 👍🏻
I know Im asking randomly but does anyone know of a way to log back into an Instagram account??
I stupidly forgot my account password. I appreciate any tricks you can give me
@Sullivan Franklin instablaster :)
@Kai Zaid I really appreciate your reply. I found the site thru google and im waiting for the hacking stuff now.
Seems to take quite some time so I will get back to you later with my results.
@Kai Zaid it did the trick and I actually got access to my account again. Im so happy!
Thank you so much you really help me out!
@Sullivan Franklin No problem :)
Excellent...
This is a fantastic video, great explanation. Helped me revise my fundamentals
Deepali ,good job ,nice explanation buddy
Good video about timing report, can you explain about OCV on timing
You're flawlessly fabulous..
Great job 👍
Hai team
1.First of all thanks for the stuff u guys place here.
2.The animated or the images you give for detailed explanation really help a lot in understanding the subject easily.
3.I want you to please update the videos on STA based on the concepts in STA-Bhaskara.
From chapter 5 to till end if you take the things placing as different videos for each topic where explaining the topics in easy way would help us a lot.
5.I am also a working Physical design engineer -,ur work and the idea of this channel is great .
6.Want you to wali through the allstages of physical design from synthesis (optional) , floorplan to routing .
7.Anyways some of the signoff checks u already started explaining.Want you to go through some more signoff checks too for to explain them too in further videos .
8.There are some tools too like starrc..primetime ....calibre ..virtuoso or Icc2 among all it would be helpful if you show the execution of starrc .. primetime ..calibre where you shall tell regarding the inputs and process we carryout in tools.
9.If anything needed I can also help ,you can contact me on mail thousif.shaik9@gmail.com or 8179898460.
10.Thanks for your hardwork .
From
Thousif shaik
Thanks shaik.
Will definitely work on your suggestions :)
Good video with clear explanations...nice work... :-)
Thanks :)
@@backtobasics5602 wlcm. Keep uploading more of these, very helpful for us .😇
Ma'am,in hold analysis we have to consider only the skew in propagated mode,as we r checking in the same/single clock edge,the jitter factor we shall not consider or add on the calculation.
Add some videos related to FinFet technology
hi , in genus i see sequential cells without clock wave form , but in innovus i dont see any such warnings , can i ignore them
great
Awesome!!!!!!!!!!!!!!!!
Nice
In that reg to reg path we have a common clock buffer so in that case cppr come into picture right.....so in that report.....no cppr value add how it's possible possible?
Because it is without considering OCV... No derate is applied here.
Derate is different cppr is different...in that cppr we will remove the common clock buffer delay only......OCV is different
OCV, Derate and CPPR all are interrelated. To account OCV in the design we give derate..and because buffers in the common clock path will have different derate values because it is common in data as well as clock path, it will add extra pessimism. To remove that extra pessimism we add CPPR.
I will soon make a video on this :)
@@backtobasics5602 in that OCV ....we accounting the PVT... variation only. In that cppr we will removing the common clock path buffer delay we make it as zero...why means....in that setup check we take as a RT path is min and AT path is max....so in the common clock path buffers.... not act at same min and max..... that..y we need remove the entire common clock path buffers delay...at zero for that only we introduce the CPPR ....?
I don't think crpr is enabled here ... Even if it were enabled, the clock network is not yet built. So it wouldn't make any difference anyway
Recovery, removal time
CPPR problem
Please explain
Hi in the Set up and Hold Time Vedio you gave 2 inequality equation for Set up and Hold time. My question is how much Positive Slack is required or how much Negative Slack is required to determine Set up and Hold Violation . They can be any number or is that fixed?
If there is negative slack, it means that's a violation.
Hi ...
Please consider if u find it correct for hold we take only noise margin not jitter we don't consider jitter in case of hold because hold check is done at same clock edge for launch and capture..
Thank you
For half-cycle hold check, you still need to consider DCD. Thanks!
In the last part data arrival time is -0.35 and data required time is 0.17, but you mentioned it as 0.35 - 0.17 = 0.18 ... why is the negative sign ignored?
can arrival time be -ve
could u please do on CMOS working
Thank you
Isn't slack = required time - arrival time = 9.55 - (-0.26) = 9.81 ??
Mam it's a nice effort... Plz put conceptual videos for how the setup and hold analysis varies for other timing path .
Thanks
Mam how to reduce congestion in placement
First check whether the congestion is due to cells or pins .
In the tool go for congestion maps and check the histogram .
So if the congestion is due to cell density then select the particular cells and then create a placement partial blockage or if it's due to pin density create keep out margin.
Later this in the PD tool you can go for reset placement and the do place_opt or refine_opt now if it's more congestion then enable congestion driven placement to active before performing place ,_opt or refine opt
Thanks better check websites bro..
@@Thousifshaik1030 very well explain.can you tell me refernces or website which you have been referring for this.
Why source latency was zero ???
+rep
Please provide mail id
backtobasics2196@gmail.com
@@backtobasics5602 Thankyou for your lectures.. Please do the lectures fastly.. Don't take this much time.. There is 1 month gap between 1 video to another.. Please make video atleast within 15 days...