5 Stage Pipeline

[@xxmemestar69xx82]

Is there a stall for the xor instruction due to the presence of dependencies?

[@toniiicarbonelll287]

great explanation!

[@georgentountou3162]

during the sub instruction shouldn't we delay one more cycle and so the table would have been: sub.... F d* d* D ?

[@hoodboykhan8003]

We are getting the value from mem to X through forwarding (there is a wire), and we only need the value in X 6:24 stage so

[@m.raflyyanuar9886]

I still don't understand the part when you delay the sub operation in the fifth cycle. Something involving memory access is still not clear in my mind. Can you please explain it to me?

[@MeANDmyPETgoat]

it needs to stall so the LW M/WB register can forward to the ID/EX register of the SUB instruction

[@raffaeleesposito5717]

@@MeANDmyPETgoat yes

[@madhusaivemulamada3556]

nice explanation

[@rauapayl4223]

Noice