DVD - Lecture 6c: Floorplanning

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 6 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 6 covers the traversal from the logical domain of RTL and Synthesis to the Physical Implementation stages of Floorplanning, Placement and Routing. This lecture focuses on Floorplanning, including Power Planning and a bit about Multi-Voltage and Hierarchical design.
Lecture 6c explains the process of floorplanning, one of the most important parts of the backend design, including methodologies, tips, and good practice when building a floorplan.
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/...
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@rogerfederer6456]

Hello Professor Teman, what is the reason behind placing the power-hungry macros away from the chip center for wire bond in the slide on Hard Macro Placement. What role does position have in the therma aspect? Whats the relation to the wire bond? Does it matter if it is a BGA?

[@rogerfederer6456]

What might be the use of a routing blockage?