YOU can produce an even bigger High to Low progation delay If the B and C nMOS in the PDN are OFF then the B and C pMOS in the PUN are ON, which means you must also consider two additional capacitances: (bad notation follows) C_ABp, the capacitance between the A and B pMOS in the PUN, and C_BCp, the capacitance between the B and C pMOS in the PUN. For the input transition: [ABCD] = [0001] -> [1001], these two capacitances, C_ABp and C_BCp, were at VDD before the transition (i.e. when [ABCD] = [0001]), but will need to be pulled down to GND after the transition. This leads to a bigger delay.
Thank you very much for your work! Just a side note, it'd be great if you can point out your mistake in a video (use a youtube memo or something) even if you correct yourself much later in the video. I just paused the video an got very confused for a while and looked for reasons online before I gave up and continued watching and found that you corrected yourself.
I had a doubt regarding pull up network when A B C are low and D only high it works why we are not taking nmos transistor D when calculating worst case as NMOS D is ON?
Are PUN delay and Low to High propagation delay the same thing? If so, I think you'd get a bigger pull up delay with the following input transition: ABCD goes from 1001 -> 1000
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My speakers were on full blast when this started but its OKAY because your velvety baritone vocals soothed me into it
you should have continued this video tutorials. your maths and our electronics knowledge would have improved a lot.
YOU can produce an even bigger High to Low progation delay
If the B and C nMOS in the PDN are OFF then the B and C pMOS in the PUN are ON, which means you must also consider two additional capacitances: (bad notation follows) C_ABp, the capacitance between the A and B pMOS in the PUN, and C_BCp, the capacitance between the B and C pMOS in the PUN. For the input transition: [ABCD] = [0001] -> [1001], these two capacitances, C_ABp and C_BCp, were at VDD before the transition (i.e. when [ABCD] = [0001]), but will need to be pulled down to GND after the transition. This leads to a bigger delay.
respected sir,
your voice is soo perfect..
at the end its 32c+20c=52c not 62 c ..ans =13rc for pull down newtwork
Thank you very much for this lecture! This helped me a lot for my IC design learning. :D
Your math blows my mind.
Dude has a golden voice !
Thanks brother it is good lecture for delay method
Fantastic video, keep the channel onnn
as w\l is 4:1 that means k = 4 so for nmos it should be r/k = r/4 right ?
Thank you very much for your work! Just a side note, it'd be great if you can point out your mistake in a video (use a youtube memo or something) even if you correct yourself much later in the video. I just paused the video an got very confused for a while and looked for reasons online before I gave up and continued watching and found that you corrected yourself.
Thanks for this video. However, towards the end, 20+32 is 52, not 62
and 62/4 is 15.5 not 31.5 xD
@@yousefmostafa4875 he divided 2 :v
Thank you for the video. Great narration. I have one question: How can you find value of k for nand or nor gate with the help of unit inverter size?
where did the resistance of D PMOS go ?
Hello friend. How do you get those expression in the start of the video? Pmos/Nmos resistances? The only parameters I have are Kp and Kn values....
I had a doubt regarding pull up network when A B C are low and D only high it works why we are not taking nmos transistor D when calculating worst case as NMOS D is ON?
from 2019 thank you
Are PUN delay and Low to High propagation delay the same thing? If so, I think you'd get a bigger pull up delay with the following input transition: ABCD goes from 1001 -> 1000
SIR from which book/resource did u learn this? I want more questions for practice! I have an exam to pass on VLSI Design
at the end of the video 62/4= 15.5 ; not 31.5..thanx for the video
THX for the video
How many times have you apologised here man 🤣
Thanks a lot br9
very very good
There's a mistake while calculation Elmore delay on the Pmos side! The capacitances between B and C is 24C and the same between A and B!
How?
lmao y'all needa chill with the math xD we're here to learn about ee!
SUPER CUTE MAN~
Made up voice is funny 🤣