32:45 The Xeon 6138P, which integrated an Icelake server XCC with an Arria 10 FPGA on the same package did make it to market. Fujitsu created servers with it, not just Intel's reference designs. It was publicly shown at mobile world congress, as NFV was a primary use case. I was the sysdebug lead, BIOS architect, and platform architect contributor on the Xeon+FPGA project as we called it at the time. We had FSB connectivity in the late 00s, and when I was hired in 2010, we brought up QPI. Skylake+FPGA implemented UPI, and there was continuity with the P-Tile on Stratix 10 and Icelake. I still look back on the core team and extended team very fondly. CXL has superseded our work, but I take some comfort in knowing that we contributed to it.
It’s not completely dead, but it’s not the bleeding edge or even the fast followers that are chasing it, and the oems are not making any significant investments. It’s something for the leaders of the commodity products that still want to scale beyond their competitors.
@@rydplrs71 - Cerebras would surely pay a huge premium for a cutting edge 450mm wafer scale engine. That would allow for - so many - more cores and so much more cache.
Thank you, Jon, for telling this story. One of the ironies for Intel is the yo-yo between LEAD and LIMITS. During the ICF era, we had a compelling technology lead that brought customers in, but leveraging it wasn't easy due to the limitations on customer pursuits. Now, the limits have been lifted with full Intel commitment to grow the business. But alas, the lead has disappeared. The foundry has a chance if Intel takes back that lead before dying in the Valley of Death.
When using cross dissolve etc. you preferrably should have the clips running during the transition as well, it's kind of distracting how the flow stops as the dissolve is applied; for example at 22:04 the clip of the terminator assembly unit is frozen until the dissolve ends. This has been prevalent in, I think, all your productions so far. Easy fix. Thanks for some of the best stuff on YT.
I've somehow never noticed until now, and now that it's been pointed out and I go through other videos I notice it all the time. I don't know whether to curse you or thank you 😅
@@redare7 How about zooming in/out as a constant percentage change, where the zoomed-out end happens extemly fast and the larger you get, the more gradual the size change seems to happen. This drives me nuts in some videos where it feels like you're about to crash into whatever's being zoomed into as the pace seems to quicken. This is a default behavior of zooming via scale in Premiere Pro at least and is very prevalent in all kinds of productions. It's very notable in The History Guy's production, for example, as he uses a lot of zoom-in for making still image slideshows appear more lively. Nothing wrong with that in itself, ofc.
Loved the video, thanks for all your hard work, especially if you’re under the weather! If you hadn’t mentioned the cold, I wouldn’t have noticed anything wrong (granted I listened to this from my phone’s speaker while making dinner, so I don’t want to disparage the work you’ve don’t in the past to provide a great audio experience). Reminds me of a useful tip my high school marching band director gave us. She said that if you ever make a mistake when moving across the field, just continue to move with confidence. No one in the audience knows where everyone is supposed to be, so if you don’t let them know something’s wrong, everything will be alright.
Taking up FPGA manufacturing was a good move, even if not a huge money maker. They are a high volume product, and having back then an energy efficiency lead was quite a competitive edge.
Sometimes these mistakes actually help the industry, especially when competitors step up and use the opportunity to create real value. I love intel, but it's never good to dominate for so long. I'm excited and invested in watching them make a comeback.
The false narrative will stop. Asianometry knows so SPEAK UP oh high one. xScale for Intel to produce a competitively priced SOC would be price < variable cost on Intel cost structure so no way that would happen proven at Bay Trail P @ and < C. xScale was also 20-bit word length and no one wanted xScale because of that regardless the Intel cost : price / margin issue. FTC Monitor Mike, former ARM employee, Marvell consultant, Cyrix, Nexgen, AMD employee, Samsung, Intel, IDT Centaur consultant this false narrative around Intel not picking up xScale corrects here. mb
As a former Intel Employee, i am interested on how well the the Company is doing and their Future. I used to Work not far from where Gordon Moore Park is located, This Site is where Intel Does most of their R&D and also has the 1st ASML NA High Aperture Tool.
@We_Are_I_Am No, I Worked for Intel at Hawthorne Farms, South of Ronler Acres. At that Time (1983-86) a lot of the Land that became Ronler Acres, was Owned by NEC off Shute Road.
I have never dealt with Intel on any direct scale, but everything I have read of them and heard of them since the 8008 days has always left an impression of arrogance. Confidence is fine. Arrogance is poison. I don't know what it will take to get that out of their system.
Kevin Barry Pepperoni + ketchup ? , or real Italian style, Fresh Tomato and Salami is better, make that in house please ! What is it you need, or are you just playing games here ?
I have to admit I never expected to be called a weirdo by a tech TH-camr in a video about foundries due to my preference towards pizzas. I'll take it though!
Back around 1995, in FAB5, we ran foundary lots on the Pentium line. Totally different litho masks. Totally different metrology. I seem to recall it was for Qualcomm.
@@Asianometry I won't try to explain it in a post, but a good start is the Free Software Foundation and look up GCC compilers/toolchains for Intel and ARM. Used to compile OS kernels from "bare metal" instruction set and machine defined by CPU core.
@@JoseLopez-hp5oo If only it were so simple. Cross compilers only work for things you still have the source code for. You would not believe just how much of our technology in the world is running binary only blobs. From games to banks, alot of companies have lost the code or were never allowed to have it in the first place. Not to mention it is not error free nor sometimes not even possible to cross compile alot of code even if you do have the source. Certain architectures simply do not have some of the low level paradigms or concepts needed to run. eg. see all of ps3 emulation. Real human cost is required to engineer around these problems
@@Asianometry The idea is that your c/c++ code can just be compiled to another architecture like ARM or Risc V. This is generally true if the code is well enough written. And lot of high quality software, especially those that already ran on multiple architectures before (like PowerPC, Sparc, ....) can do that. But a lot of software was not written that well. Apple's first transition from PowerPC to Intel x86 was also plagued a lot by this. But the second transition to ARM was a lot smoother because very old software already had a transition that eliminated these kinds of bugs from the first transition and new software was often already multiplatform (e.g. also running on multiple phone). In a way it is similar to foundries. A thing that Ian Cutress (@techtechpotato) stressed is that in the past, you needed to use Intel's own software to build for Intel's fab. Only recently they started really supporting industry standard software like from Synopsis. But it is only a first step to be able to use Intel as alternative Fab without having to redo the whole design in a completely different software.
Cross compiler is used to compile software for another platform. Example, a compiler running on an Intel x86 compiling source code into binaries that can be run on an ARM chip, this is called cross compiler.
Oh, I remember ICF. And what is making current Intel Foundries bad is that they won't have "industry standard" Development Software until 18A. There are of course other things that might make NVIDIA or AMD or some others hesitate to approach Intel Foundry, but there are other players who would like to have choice on leading edge node other than TSMC (and maybe Samsung - if it's not as leading edge). And this makes it harder for Intel to get customers. Not to mention huge amounts of money would be made on services other than leading edge process node. So it might be few years AFTER 18A is released that it will start to make money.
@@BellJH I think they are working on some kind of translation patch for 3 and 2 (I have to check the naming scheme, because it's also known as 20A and might be half-node or something - I don't remember after all night not sleeping) - yes. And possibly they might have working standard industry development kits for those - if they manage everything perfectly. The issue is - if it's "translation layer" - how good is it going to be? And if they do manage to go with standards on launch day - that might be an issue for Intel engineering teams that are already locking in designs for those nodes. It will be a miracle if they won't have some issues because of that. Either in their products or in their capability of working as foundry for companies not affiliated with them at the moment. I guess it will depend a lot on how well the foundry team will work and be supported for changes in node libraries. I have to go and remove the snow from my car and attempt to drive out to the shop. I will fact check myself later, because ATM I'm working purely from memory, so it's quite plausible I got something wrong.
You are sorely mistaken. Both Synopsys and Cadence flows were supported by ICF on then 10nm process node. Intel internal design tools were mostly restricted to Big Core design and for a good reason.
@@pavelrott311 From Intel: "Intel announces expanded process roadmap, customers and ecosystem partners to deliver on ambition to be the No. 2 foundry by 2030." "SAN JOSE, Calif., Feb. 21, 2024 - Intel Corp. (INTC) today launched Intel Foundry as a more sustainable systems foundry business designed for the AI era and announced an expanded process roadmap designed to establish leadership into the latter part of this decade. The company also highlighted customer momentum and support from ecosystem partners - including Synopsys, Cadence, Siemens and Ansys - who outlined their readiness to accelerate Intel Foundry customers’ chip designs with tools, design flows and IP portfolios validated for Intel’s advanced packaging and Intel 18A process technologies." "IP and EDA Vendors Declare Readiness for Intel Process and Packaging Designs Intellectual property and electronic design automation (EDA) partners Synopsys, Cadence, Siemens, Ansys, Lorentz and Keysight disclosed tool qualification and IP readiness to enable foundry customers to accelerate advanced chip designs on Intel 18A, which offers the foundry industry’s first backside power solution. These companies also affirmed EDA and IP enablement across Intel node families. At the same time, several vendors announced plans to collaborate on assembly technology and design flows for Intel’s embedded multi-die interconnect bridge (EMIB) 2.5D packaging technology. These EDA solutions will ensure faster development and delivery of advanced packaging solutions for foundry customers." So the part where you say: "Intel internal design tools were mostly restricted to Big Core design" - isn't exactly accurate. Or at least this "mostly" part is very important. Many technologies that enable nodes to be "useful" for designing SoC's were also restricted. So if for example you wanted to use Intel 4 node - so you'd start design like 2 years ago, you would be pretty limited, unless you were designing something quite simple. Of course this is evolving. Some of the capabilities are being added. ATM I'm very busy, so I can't find exact source - but there was roadmap from Intel that did show (I think 18A) as the one that is fully compatible with design tools and allows use of basically all transistors in the node (which doesn't mean they won't be behind license, but that's a bit different). There is also recent Video from Ian Cutress talking about it. There are some Intel documents that even indicate that 14A will be the first to use full Intel Foundries ASAT. Again - I will later have time to check exact sources, but given that Synopsys, Cadence, Siemens and Ansys (I think) in April 2024 said that from now on you will be able to design stuff for Intel Foundries on our products shows that there was a gap and divergence between Intel and everyone else. I'll try to get back to you when I do have time to re-check my sources. And of course it's possible that I'm completely wrong. But most bigger customers start to get on board with IF with 18A and 14A nodes. And the reason for it is thought to partially be that Intel was making it hard for previous nodes to be used by others. Including design systems and standards.
@@pavelrott311 OK. One of the smaller stuff I found - in 2025 they will add: Physical Verification for Foveros to Cadence Pegasus and Siemens Calibre. Thermal compatibility for both Foveros and EMIB to Ansys RHSC-ET and Synopsys Kelvin. Most of their work though is for some variants of Intel 3, for Intel 18A, Intel 16 and Intel 14A. Intel 4 has much less support. And most of the support for node I mentioned was added throughout 2024. Which is why most optimistic big customers talk about timeline of 2027+ (and more realistic ones - 2029). Given that Intel already has test chips for 18A, this does leave those clients behind. Though indeed I found that Synopsys had better support than most other firms. And indeed in certain areas Intel 3 is also mentioned as being supported. That's still an issue though - design of a chip can easily take 4-5 years if it's complex one. Assuming that Intel's timeline holds, you should be able to start (fully) designing a chip for Intel 3 that uses Foveros and/or EMIB in the middle of 2025... which given that Intel has working prototypes in that node - it's not a great look for a foundry. And yes, Daniel Nenni does say that for Intel it's not as terrible as it sounds.... but for clients that aren't at Intel - this still leaves them at the mercy of Intel. Though he does say Synopsys and Cadence have the best support from outside companies. The thing is that Intel prioritized it's own especially after ICF failed and they started using their own EDA. Synopsys and some other companies had some support, but not for the most enticing parts of Intel Technology (and EMIB and Foveros are really important if you want to do anything chiplet based). And Intel had huge leverage over others with how they could design chips. And they didn't care that it was much easier to design for TSMC. And still is.
Has @Asianometry ever done a video on how companies work in collaboration with chip producers? Not sure if there is any collaboration though, maybe they just provide a schematic/design/photomask or something and that is it, but if there if a feedback cycle, that would be interesting to get an insight into how that might look like.
If you want to make any semi-custom chip (so using existing company IP and your own IP - Sony might be example with PS5, where most of the stuff is AMD's, but there is also Sony IP) - they have to collaborate heavily. Once they choose the Foundry (which is usually one of the first choices to make), they also work with them. Because they need to design their chips in such a way that Fab can produce it. So you try to use as much of what types of transistors foundry offers - but sometimes it's impossible and foundry has to add additional types of transistors to it's list (and then there is whole question, who's IP said transistors are - whether foundry can also use them for other designs etc.). If you make custom chip than it's only your IP and the foundry - much riskier, but if you're lucky and competent, you might be able to have slightly less costs on collaboration. Though such collaboration brings a lot of experienced engineers etc. so there are few companies that decide to build their own chips right from the start, unless they are very simple. And there was a video from Asianometry on IDM or EDM as those things are called - which are basically Companies and Foundries programs to design chip using their standard libraries. So that you can see if you can make such a chip and if there are changes needed, is it a better decision to ask foundry to add additional libraries (costly) or whether you cut out said capability from your chip (capability loss) or if it's possible to design what you want in sub-optimal manner using standard libraries (you have capability and the cost will likely be in performance and/or power use and/or surface area of the chip). Sorry if it's a bit complicated. I tried to write as short of an answer as possible. This is still simplified, but if you didn't know how those things worked it should give you decent idea of how it does work.
This whole foundry concept reminds me of contract manufacturing in BioTech, Pharmaceutical industry. There are also issues in producing for clients but also taking over when patents expire in having own products. Especially when the original product owner is not interested in staying in the market with a new no-name product offering the same as the original product.
That's a great story, well laid out as usual. I take from this that IFS must really become separated from x86 architecture, otherwise the risk of competition with customers will always be a giant obstacle to IFS.
Excellent, as usual. And your final advices are just to the point. If only Intel top management could hear them in loop 5mns every morning for at least a week 😂
Always the best channel I've subbed to. But you do absolutely not need to work the algorithm so hard. I'm sure so many of your subscribers here have the Bell icon on. I would never miss your vids, not in years now... Just look after yourself. If you're not up to it, that's absolutely cool. We will be here anyway.... 👍
I’m a bit surprised by repeated statement - made without corroboration but repeated several times - that ICF “wasn’t ready for prime time” (meaning to support large customer like Apple.) That’s just misleading - on 14nm node ICF would be able to serve its customers’ needs,’it had both expertise and means to do so. 10nm node delay was out of its control but the statement that it wasn’t ready doesn’t hold water.
Seems like the 'taking care of business' end of things, demands as much, or more, effort & ;tricky maneuverings and timely trading, and placing all of the puzzle pieces together, than the technical side of making chips.
Please discuss superconducting wires and cables. How they are made. Also it would be neat to see you discuss rare earth magnets. how they are made, and how the process differs for each grade of magnet. Other ideas include scintillator crystals, solid-state photo multipliers (sipm's) Shit....hamamatsu as a company and their products in general could be an entire Year's worth of insanely interesting videos. Also the crazy exotic materials and semiconductor adjacent stuff.... as it pertains to particle colliders... and they're insanely engineered scifi-esque sensor technology.
I know you said it's a cold. But I'm gonna say this just in case...please don't do that TH-cam thing that many channels do to unnaturally prolong the video duration. Your information density is the reason I love this channel. Don't do it man.
@gikigill788 they can definetly continue to screw up, but they have a much bigger window to fix things than most. It takes a special kind of stupid to completely break a place with as much going for it as intel. I can't tell the future but that's my view on it. Guess I'll wait and see if this comment ages like wine or milk lol.
Their only opportunity was Pat Gelsinger, the comeback CEO engineer. Now the next CEO will divest (with Commerce approval) the IFS Foundry. It's too late.
@@MrSpiritmonger Ofcourse they should divest it. Right now, they still compete with their own costumers, that wont work in the long run. As soon as 18A is finished and can attract enough customers to finance itself, Intel Products and Intel Foundry should become two separate companies.
You probably haven't heard of Intel's FLEXlogic family of FPGAs which existed for a short time in the 1990s. If I remember right they sold the family to Altera, which, rather ironically, was purchased by Intel not long ago.
Your voice is notably nicer in this video, I thought you had a new mic or filter that takes out the slightly harsh part of your accent. (Some tones in east asian accents can be harsh to an american native-english ear. It is like the opposite of relaxed, but with mo reason for the stress.)
PG directed Intel to adopt the external design tools used by the competition: Synopsys, Cadence, et al. Intel has now demonstrated the ability to package different process tiles, including tiles from TSM. His plan was to make Intel IP tiles available. They have demonstrated potentially valuable IP ... PCIE5, CXL2.0, copackaged optic solutions, integrated GPUs , WIFI7, TB5. Ultra Ethernet, PCIE6, CXL 3.0 are coming soon.
I think the key point for Intel is to control costs. Even that means less custom foundry revenue. Treats its foundry assets as its OWN insurance for geo-instability. If you only pay for your own insurance and not pay others, you save costs.
Xyang Why you need controlled costs, you are NOT the west i see. Who owns the patents and Code ! TSMC owns nothing, only producing what other need ! IS THAT SMART ? WHY GO FABLESS ?
"10 year endeavour". Except the board only have forward vision measured in quarters. I have been an Intel fan since the 90s but I seriously wonder if they'll even be around by 2030. Good luck to them :(
calzoni, cant go wrong with a calzoni. Great video. I hope all these capabilities doesn't contribute to unrestricted time travel, that would be bad.. Unless it saves carbon emissions I guess, lol.. hope your feeling better in no time.
Intel did not have any parallel process development back in the 2000s/2010s. Two leapfrogging teams is how TSMC did/still does their development. Intel had a development model similar to an automobile assembly line. Academic research -> components research -> pathfinding -> development -> ramp -> transfer. If a technology got held up at any point in the line, everything upstream of that bottleneck grinds to a halt. Chiphistory has an interview with Sunlin Chou explaining the development of the process development he implemented at intel back when Intel was transitioning from a technological laggard to a leader. One nice bit of ICF's legacy is P1222 (22FFL). This technology would go onto serve as the basic skeleton for intel 16/16-E and served as a great learning environment for Intel Foundry with their collaboration with MediaTek.
I heard some ominous slamming noise in the audio track for this video, are you trapped in the TSMC dungeons? If you dont reply to this comment I will consider you to be under threat and send an extraction team.
If a foundry like intel's or one of the new TSMC foundries is considered out of date, is it just a matter of replacing the lithography machines to use the latest nodes?
You’ve got two options. You keep the fab for that specific node and keep it running as a legacy node, or you re-tool the foundry for the new node. Re-tooling is expensive so only really done if necessary AFAIK
@BellJH yeah I sort of got that, I guess what I meant was, can you just replace the main machines on the floor and continue business as usual, or is it an almost 100% refit?
Don't something as gate last, was simply that they was lucky? Because from what I remember it wasn't obvious choice. 4:10 sorry, but iPhone don't have Intel, because they decision, not architecture
I think people are really sleeping on not just IFS, but the environment that would lead IFS to be conducive. We are entering an environment that will be increasingly hostile to free trade and outsourcing, and Intel need to take that as a multiplier to competitive capabilities. I feel like many are not seeing it, and when Jensen Huang says that he has yet to visit Trump because "He hasn't received an invitation", I sense the very same complacency that got Intel in the spot it is in today.
could you make a special of introducing intel leaders and board of directors? I still see this as a bad/dump leadership making, decision, short sighted that cause the whole Once Great Intel FALL.
Damn you for the food analogies. I'm watching this in bed after already brushing my teeth and you are making me hungry. I'll come back tomorrow when I'm less famished.
32:45 The Xeon 6138P, which integrated an Icelake server XCC with an Arria 10 FPGA on the same package did make it to market. Fujitsu created servers with it, not just Intel's reference designs. It was publicly shown at mobile world congress, as NFV was a primary use case.
I was the sysdebug lead, BIOS architect, and platform architect contributor on the Xeon+FPGA project as we called it at the time. We had FSB connectivity in the late 00s, and when I was hired in 2010, we brought up QPI. Skylake+FPGA implemented UPI, and there was continuity with the P-Tile on Stratix 10 and Icelake.
I still look back on the core team and extended team very fondly. CXL has superseded our work, but I take some comfort in knowing that we contributed to it.
Thank you for the video. I love all your photolithography specials. We all hope you feel better soon.
Wow... Thank you. I've had this question for nearly 20 years. Many many thanks for taking the time and effort to answer so effectively
Relax on the sound of your voice, it is the content of your message that counts to us.
Get well soon!
Also, the effort to find all these quotes and details is astonishing. Thank you for the insight in this and many other episodes!
No 450mm pizza pies sorry
It’s not completely dead, but it’s not the bleeding edge or even the fast followers that are chasing it, and the oems are not making any significant investments. It’s something for the leaders of the commodity products that still want to scale beyond their competitors.
@@rydplrs71 - Cerebras would surely pay a huge premium for a cutting edge 450mm wafer scale engine. That would allow for - so many - more cores and so much more cache.
You gonna eat that, 😝
Feel better soon! Thank you for the video as always.
Thank you for taking the time to explain the issues so the lay man can understand.
Before the note about the cold I could have sworn the audio was slowed by 5-10% or you were experimenting with an AI voice replication.
I was thinking the same. Video could have been 7 minutes shorter is delivered with the usual enthusiasm.
Oh the longer format is good for me. @rwired
Thank you, Jon, for telling this story. One of the ironies for Intel is the yo-yo between LEAD and LIMITS. During the ICF era, we had a compelling technology lead that brought customers in, but leveraging it wasn't easy due to the limitations on customer pursuits. Now, the limits have been lifted with full Intel commitment to grow the business. But alas, the lead has disappeared. The foundry has a chance if Intel takes back that lead before dying in the Valley of Death.
When using cross dissolve etc. you preferrably should have the clips running during the transition as well, it's kind of distracting how the flow stops as the dissolve is applied; for example at 22:04 the clip of the terminator assembly unit is frozen until the dissolve ends.
This has been prevalent in, I think, all your productions so far. Easy fix.
Thanks for some of the best stuff on YT.
At 21:33 you can see this happening at both the end of clip A and the start of B. Double stop.
I've somehow never noticed until now, and now that it's been pointed out and I go through other videos I notice it all the time. I don't know whether to curse you or thank you 😅
@@elodiefiorella4750 Let me tell you about motion artifacts in video. You will indeed curse me out once I teach you to notice it.
@@redare7 How about zooming in/out as a constant percentage change, where the zoomed-out end happens extemly fast and the larger you get, the more gradual the size change seems to happen.
This drives me nuts in some videos where it feels like you're about to crash into whatever's being zoomed into as the pace seems to quicken. This is a default behavior of zooming via scale in Premiere Pro at least and is very prevalent in all kinds of productions.
It's very notable in The History Guy's production, for example, as he uses a lot of zoom-in for making still image slideshows appear more lively. Nothing wrong with that in itself, ofc.
I've noticed this several times, but would feel bad bringing it up 😅
I do hope he fixes it, it seems obvious
Loved the video, thanks for all your hard work, especially if you’re under the weather! If you hadn’t mentioned the cold, I wouldn’t have noticed anything wrong (granted I listened to this from my phone’s speaker while making dinner, so I don’t want to disparage the work you’ve don’t in the past to provide a great audio experience).
Reminds me of a useful tip my high school marching band director gave us. She said that if you ever make a mistake when moving across the field, just continue to move with confidence. No one in the audience knows where everyone is supposed to be, so if you don’t let them know something’s wrong, everything will be alright.
Taking up FPGA manufacturing was a good move, even if not a huge money maker. They are a high volume product, and having back then an energy efficiency lead was quite a competitive edge.
Wow Otellini was complacent on the Arm threat
Sometimes these mistakes actually help the industry, especially when competitors step up and use the opportunity to create real value. I love intel, but it's never good to dominate for so long. I'm excited and invested in watching them make a comeback.
Me too.....makes me wonder if a similar reversal will happen with NVIDIA.,.or with TSMC?
The false narrative will stop. Asianometry knows so SPEAK UP oh high one. xScale for Intel to produce a competitively priced SOC would be price < variable cost on Intel cost structure so no way that would happen proven at Bay Trail P @ and < C. xScale was also 20-bit word length and no one wanted xScale because of that regardless the Intel cost : price / margin issue. FTC Monitor Mike, former ARM employee, Marvell consultant, Cyrix, Nexgen, AMD employee, Samsung, Intel, IDT Centaur consultant this false narrative around Intel not picking up xScale corrects here. mb
@@stevengill1736no, Nvidia and TSMC are run by engineers, not a marketing/finance types like Otellini and current co-CEOs.
@@MrSpiritmonger They're run by engineers *right now*. We'll see if that changes like it did for other companies.
One of my favourite videos yet! I would love a deep dive on what went wrong with 10 nm
All this video did was make me order a pizza LOL. Fantastic work Asianometry!
As a former Intel Employee, i am interested on how well the the Company is doing and their Future.
I used to Work not far from where Gordon Moore Park is located, This Site is where Intel Does most of their R&D and also has the 1st ASML NA High Aperture Tool.
You worked at Ronler Acres? I remember my time in D1C & D1D
@We_Are_I_Am No, I Worked for Intel at Hawthorne Farms, South of Ronler Acres. At that Time (1983-86) a lot of the Land that became Ronler Acres, was Owned by NEC off Shute Road.
Get well soon!
Awesome episode. Really drives the point home of the importance of aligning incentives, and combating hubris.
Intel was so full of itself it was almost unbelievable. separately, I don't want any pepperoni on my damn pizza!
I have never dealt with Intel on any direct scale, but everything I have read of them and heard of them since the 8008 days has always left an impression of arrogance. Confidence is fine. Arrogance is poison. I don't know what it will take to get that out of their system.
Kevin Barry
Pepperoni + ketchup ? , or real Italian style, Fresh Tomato and Salami is better, make that in house please !
What is it you need, or are you just playing games here ?
@@grizwoldphantasia5005 Why break that domancy x86 by law, you need that monopoly back ?
Who needs that Old Intel Back, are you Andy Groves old too ?
This might be my fav story so far. Right up there with the video on the decline of Iranian births.
i always felt the importance of learning the history in order to understand the technology. thanks for all the history lessons through these years :)
3:24 “Flash Applications”? That did it.
Man, it hurt when Intel dropped their manufacturing site investment in Poland.
I was similarly surprised by the biography about Morris Chang. An English translation would be lovely, I’d definitely buy.
Keep up the great work buddy.
Wow, Great review ... that was really informative!
I have to admit I never expected to be called a weirdo by a tech TH-camr in a video about foundries due to my preference towards pizzas. I'll take it though!
Back around 1995, in FAB5, we ran foundary lots on the Pentium line.
Totally different litho masks.
Totally different metrology.
I seem to recall it was for Qualcomm.
I loved the Atom netbooks and I wish they'd make a comeback.
Bring back 4 Watt TDP Atoms!
Hardware guy never heard of a cross compiler..rewriting not needed. Perhaps that would make a great video, GCC and the free software foundation.
Cross compiler? Never heard of it
@@Asianometry I won't try to explain it in a post, but a good start is the Free Software Foundation and look up GCC compilers/toolchains for Intel and ARM. Used to compile OS kernels from "bare metal" instruction set and machine defined by CPU core.
@@JoseLopez-hp5oo If only it were so simple. Cross compilers only work for things you still have the source code for. You would not believe just how much of our technology in the world is running binary only blobs. From games to banks, alot of companies have lost the code or were never allowed to have it in the first place.
Not to mention it is not error free nor sometimes not even possible to cross compile alot of code even if you do have the source. Certain architectures simply do not have some of the low level paradigms or concepts needed to run. eg. see all of ps3 emulation. Real human cost is required to engineer around these problems
@@Asianometry The idea is that your c/c++ code can just be compiled to another architecture like ARM or Risc V. This is generally true if the code is well enough written. And lot of high quality software, especially those that already ran on multiple architectures before (like PowerPC, Sparc, ....) can do that. But a lot of software was not written that well.
Apple's first transition from PowerPC to Intel x86 was also plagued a lot by this. But the second transition to ARM was a lot smoother because very old software already had a transition that eliminated these kinds of bugs from the first transition and new software was often already multiplatform (e.g. also running on multiple phone).
In a way it is similar to foundries. A thing that Ian Cutress (@techtechpotato) stressed is that in the past, you needed to use Intel's own software to build for Intel's fab. Only recently they started really supporting industry standard software like from Synopsis. But it is only a first step to be able to use Intel as alternative Fab without having to redo the whole design in a completely different software.
Cross compiler is used to compile software for another platform. Example, a compiler running on an Intel x86 compiling source code into binaries that can be run on an ARM chip, this is called cross compiler.
Great video. I hope to hear more about the Intel 10 nanometre story sometime as it appears to be defining for multiple industries.
yessss! I love when new Asianometry drops! Its my favorite TH-cam channel
Wonderful presentation and video. You are an amazing youtube creator.
Oh, I remember ICF.
And what is making current Intel Foundries bad is that they won't have "industry standard" Development Software until 18A. There are of course other things that might make NVIDIA or AMD or some others hesitate to approach Intel Foundry, but there are other players who would like to have choice on leading edge node other than TSMC (and maybe Samsung - if it's not as leading edge). And this makes it harder for Intel to get customers. Not to mention huge amounts of money would be made on services other than leading edge process node. So it might be few years AFTER 18A is released that it will start to make money.
I think they are working to get at least Intel 3 on industry standard development kits as well
@@BellJH I think they are working on some kind of translation patch for 3 and 2 (I have to check the naming scheme, because it's also known as 20A and might be half-node or something - I don't remember after all night not sleeping) - yes. And possibly they might have working standard industry development kits for those - if they manage everything perfectly. The issue is - if it's "translation layer" - how good is it going to be? And if they do manage to go with standards on launch day - that might be an issue for Intel engineering teams that are already locking in designs for those nodes. It will be a miracle if they won't have some issues because of that. Either in their products or in their capability of working as foundry for companies not affiliated with them at the moment. I guess it will depend a lot on how well the foundry team will work and be supported for changes in node libraries.
I have to go and remove the snow from my car and attempt to drive out to the shop. I will fact check myself later, because ATM I'm working purely from memory, so it's quite plausible I got something wrong.
You are sorely mistaken. Both Synopsys and Cadence flows were supported by ICF on then 10nm process node. Intel internal design tools were mostly restricted to Big Core design and for a good reason.
@@pavelrott311 From Intel:
"Intel announces expanded process roadmap, customers and ecosystem partners to deliver on ambition to be the No. 2 foundry by 2030."
"SAN JOSE, Calif., Feb. 21, 2024 - Intel Corp. (INTC) today launched Intel Foundry as a more sustainable systems foundry business designed for the AI era and announced an expanded process roadmap designed to establish leadership into the latter part of this decade. The company also highlighted customer momentum and support from ecosystem partners - including Synopsys, Cadence, Siemens and Ansys - who outlined their readiness to accelerate Intel Foundry customers’ chip designs with tools, design flows and IP portfolios validated for Intel’s advanced packaging and Intel 18A process technologies."
"IP and EDA Vendors Declare Readiness for Intel Process and Packaging Designs
Intellectual property and electronic design automation (EDA) partners Synopsys, Cadence, Siemens, Ansys, Lorentz and Keysight disclosed tool qualification and IP readiness to enable foundry customers to accelerate advanced chip designs on Intel 18A, which offers the foundry industry’s first backside power solution. These companies also affirmed EDA and IP enablement across Intel node families.
At the same time, several vendors announced plans to collaborate on assembly technology and design flows for Intel’s embedded multi-die interconnect bridge (EMIB) 2.5D packaging technology. These EDA solutions will ensure faster development and delivery of advanced packaging solutions for foundry customers."
So the part where you say: "Intel internal design tools were mostly restricted to Big Core design" - isn't exactly accurate. Or at least this "mostly" part is very important. Many technologies that enable nodes to be "useful" for designing SoC's were also restricted. So if for example you wanted to use Intel 4 node - so you'd start design like 2 years ago, you would be pretty limited, unless you were designing something quite simple. Of course this is evolving. Some of the capabilities are being added.
ATM I'm very busy, so I can't find exact source - but there was roadmap from Intel that did show (I think 18A) as the one that is fully compatible with design tools and allows use of basically all transistors in the node (which doesn't mean they won't be behind license, but that's a bit different). There is also recent Video from Ian Cutress talking about it.
There are some Intel documents that even indicate that 14A will be the first to use full Intel Foundries ASAT.
Again - I will later have time to check exact sources, but given that Synopsys, Cadence, Siemens and Ansys (I think) in April 2024 said that from now on you will be able to design stuff for Intel Foundries on our products shows that there was a gap and divergence between Intel and everyone else.
I'll try to get back to you when I do have time to re-check my sources. And of course it's possible that I'm completely wrong. But most bigger customers start to get on board with IF with 18A and 14A nodes. And the reason for it is thought to partially be that Intel was making it hard for previous nodes to be used by others. Including design systems and standards.
@@pavelrott311 OK. One of the smaller stuff I found - in 2025 they will add:
Physical Verification for Foveros to Cadence Pegasus and Siemens Calibre.
Thermal compatibility for both Foveros and EMIB to Ansys RHSC-ET and Synopsys Kelvin.
Most of their work though is for some variants of Intel 3, for Intel 18A, Intel 16 and Intel 14A. Intel 4 has much less support. And most of the support for node I mentioned was added throughout 2024. Which is why most optimistic big customers talk about timeline of 2027+ (and more realistic ones - 2029). Given that Intel already has test chips for 18A, this does leave those clients behind. Though indeed I found that Synopsys had better support than most other firms. And indeed in certain areas Intel 3 is also mentioned as being supported.
That's still an issue though - design of a chip can easily take 4-5 years if it's complex one. Assuming that Intel's timeline holds, you should be able to start (fully) designing a chip for Intel 3 that uses Foveros and/or EMIB in the middle of 2025... which given that Intel has working prototypes in that node - it's not a great look for a foundry. And yes, Daniel Nenni does say that for Intel it's not as terrible as it sounds.... but for clients that aren't at Intel - this still leaves them at the mercy of Intel. Though he does say Synopsys and Cadence have the best support from outside companies.
The thing is that Intel prioritized it's own especially after ICF failed and they started using their own EDA. Synopsys and some other companies had some support, but not for the most enticing parts of Intel Technology (and EMIB and Foveros are really important if you want to do anything chiplet based). And Intel had huge leverage over others with how they could design chips. And they didn't care that it was much easier to design for TSMC. And still is.
Hope you get better! Love the video.
These food metaphors are getting out of hand! :o
Making me hungry......oh yeah, near dinnertime....
Intel Thru Time: 😊🤫😁😂😮🤔😨😭
Can you do a video about how Samsung's foundry was able to balance core business with that of its partners compared to Intel's?
At least one generation of HP's PA-RISC architecture was fabricated by Intel.
You sound sick, hope you feel better soon.
6:48 I like how the Calzone is the weird pizza, when the blueberry dessert pizza (blech) is on screen!
Has @Asianometry ever done a video on how companies work in collaboration with chip producers? Not sure if there is any collaboration though, maybe they just provide a schematic/design/photomask or something and that is it, but if there if a feedback cycle, that would be interesting to get an insight into how that might look like.
If you want to make any semi-custom chip (so using existing company IP and your own IP - Sony might be example with PS5, where most of the stuff is AMD's, but there is also Sony IP) - they have to collaborate heavily. Once they choose the Foundry (which is usually one of the first choices to make), they also work with them. Because they need to design their chips in such a way that Fab can produce it. So you try to use as much of what types of transistors foundry offers - but sometimes it's impossible and foundry has to add additional types of transistors to it's list (and then there is whole question, who's IP said transistors are - whether foundry can also use them for other designs etc.).
If you make custom chip than it's only your IP and the foundry - much riskier, but if you're lucky and competent, you might be able to have slightly less costs on collaboration. Though such collaboration brings a lot of experienced engineers etc. so there are few companies that decide to build their own chips right from the start, unless they are very simple.
And there was a video from Asianometry on IDM or EDM as those things are called - which are basically Companies and Foundries programs to design chip using their standard libraries. So that you can see if you can make such a chip and if there are changes needed, is it a better decision to ask foundry to add additional libraries (costly) or whether you cut out said capability from your chip (capability loss) or if it's possible to design what you want in sub-optimal manner using standard libraries (you have capability and the cost will likely be in performance and/or power use and/or surface area of the chip).
Sorry if it's a bit complicated. I tried to write as short of an answer as possible. This is still simplified, but if you didn't know how those things worked it should give you decent idea of how it does work.
This whole foundry concept reminds me of contract manufacturing in BioTech, Pharmaceutical industry. There are also issues in producing for clients but also taking over when patents expire in having own products. Especially when the original product owner is not interested in staying in the market with a new no-name product offering the same as the original product.
That's a great story, well laid out as usual.
I take from this that IFS must really become separated from x86 architecture,
otherwise the risk of competition with customers will always be a giant obstacle to IFS.
Great narration speed. Really drives the cadence of your topic.
Good Synopsys
Excellent, as usual.
And your final advices are just to the point.
If only Intel top management could hear them in loop 5mns every morning for at least a week 😂
Sorry you have a cold. Have some tea with honey. Stay off the mic for a while....
indeed!
Mushroom mix blends, all local harvests from grocery, hemp seed, lemon balm tea.
adding ginger also helps
get well soon @asianometry
Wash down some dayquil with whisky, honey, and lemon. Chicken soup if you're hungry
My thoughts exactly.....
Always the best channel I've subbed to. But you do absolutely not need to work the algorithm so hard. I'm sure so many of your subscribers here have the Bell icon on. I would never miss your vids, not in years now...
Just look after yourself. If you're not up to it, that's absolutely cool. We will be here anyway.... 👍
Outstanding analysis, thank you.
My feed was full of food videos and they were making me hungry so I'm like, I need a non food video to watch... So I clicked this. Thanks.
Awesome video. Hope you feel better soon.
Good one! Thanks. Get well soon.
What was up with the jumpscare before 2:40?
Another fine display of history, made in order to build wisdom. Thanks.
I’m a bit surprised by repeated statement - made without corroboration but repeated several times - that ICF “wasn’t ready for prime time” (meaning to support large customer like Apple.)
That’s just misleading - on 14nm node ICF would be able to serve its customers’ needs,’it had both expertise and means to do so. 10nm node delay was out of its control but the statement that it wasn’t ready doesn’t hold water.
Seems like the 'taking care of business' end of things, demands as much, or more, effort & ;tricky maneuverings and timely trading, and placing all of the puzzle pieces together, than the technical side of making chips.
Please discuss superconducting wires and cables. How they are made.
Also it would be neat to see you discuss rare earth magnets. how they are made, and how the process differs for each grade of magnet.
Other ideas include scintillator crystals, solid-state photo multipliers (sipm's)
Shit....hamamatsu as a company and their products in general could be an entire Year's worth of insanely interesting videos.
Also the crazy exotic materials and semiconductor adjacent stuff.... as it pertains to particle colliders... and they're insanely engineered scifi-esque sensor technology.
I know you said it's a cold. But I'm gonna say this just in case...please don't do that TH-cam thing that many channels do to unnaturally prolong the video duration.
Your information density is the reason I love this channel.
Don't do it man.
Adaxum’s DeFi potential feels real.
Sentence repair: "...it was less a question of ability than rather those processes being in no shape to ..."
Intel has all the opportunity to make a comeback, they need only make an effort. I see this going like how GE did when they dropped to $5 per share.
Wasn't that what Pat Gelsinger was supposed to be doing? What's up with their board of directors? It's too bad.....
If they are going to squander all profits in share buybacks instead of reinvesting, what's the point?
@gikigill788 they can definetly continue to screw up, but they have a much bigger window to fix things than most. It takes a special kind of stupid to completely break a place with as much going for it as intel. I can't tell the future but that's my view on it. Guess I'll wait and see if this comment ages like wine or milk lol.
Their only opportunity was Pat Gelsinger, the comeback CEO engineer. Now the next CEO will divest (with Commerce approval) the IFS Foundry. It's too late.
@@MrSpiritmonger Ofcourse they should divest it. Right now, they still compete with their own costumers, that wont work in the long run. As soon as 18A is finished and can attract enough customers to finance itself, Intel Products and Intel Foundry should become two separate companies.
You probably haven't heard of Intel's FLEXlogic family of FPGAs which existed for a short time in the 1990s. If I remember right they sold the family to Altera, which, rather ironically, was purchased by Intel not long ago.
I have learnt so much from your videos, I can’t thank you enough for making such engaging and interesting content.
If you’re serious about DeFi, Adaxum should be on your radar. Joined the presale for the best deal!
Your voice is notably nicer in this video, I thought you had a new mic or filter that takes out the slightly harsh part of your accent.
(Some tones in east asian accents can be harsh to an american native-english ear. It is like the opposite of relaxed, but with mo reason for the stress.)
PG directed Intel to adopt the external design tools used by the competition: Synopsys, Cadence, et al. Intel has now demonstrated the ability to package different process tiles, including tiles from TSM. His plan was to make Intel IP tiles available. They have demonstrated potentially valuable IP ... PCIE5, CXL2.0, copackaged optic solutions, integrated GPUs , WIFI7, TB5. Ultra Ethernet, PCIE6, CXL 3.0 are coming soon.
I think the key point for Intel is to control costs. Even that means less custom foundry revenue. Treats its foundry assets as its OWN insurance for geo-instability. If you only pay for your own insurance and not pay others, you save costs.
Xyang
Why you need controlled costs, you are NOT the west i see.
Who owns the patents and Code !
TSMC owns nothing, only producing what other need !
IS THAT SMART ?
WHY GO FABLESS ?
Your channel is great!!
That's not a ceramic package- it's FC-BGA (Flip Chip-Ball Grid Array).
"10 year endeavour". Except the board only have forward vision measured in quarters. I have been an Intel fan since the 90s but I seriously wonder if they'll even be around by 2030. Good luck to them :(
You sound terrible. Hope you get to feeling better. Thanks for the video.
06:51 _thank you_ for not going for the "pineapple" cheap shot.
Also, TIL I'm a weirdo. :D
Instructions unclear. Used pizza sauce instead of thermal paste and now my PC is overheating.
Thank you.
get well soon.
Get some rest. Thanks for another interesting video.
Get well!
calzoni, cant go wrong with a calzoni. Great video. I hope all these capabilities doesn't contribute to unrestricted time travel, that would be bad.. Unless it saves carbon emissions I guess, lol.. hope your feeling better in no time.
Intel did not have any parallel process development back in the 2000s/2010s. Two leapfrogging teams is how TSMC did/still does their development. Intel had a development model similar to an automobile assembly line. Academic research -> components research -> pathfinding -> development -> ramp -> transfer. If a technology got held up at any point in the line, everything upstream of that bottleneck grinds to a halt. Chiphistory has an interview with Sunlin Chou explaining the development of the process development he implemented at intel back when Intel was transitioning from a technological laggard to a leader.
One nice bit of ICF's legacy is P1222 (22FFL). This technology would go onto serve as the basic skeleton for intel 16/16-E and served as a great learning environment for Intel Foundry with their collaboration with MediaTek.
Oh man I want a good calzone now😂
.. Is there an impending cross-over with YT: "Chinese cooking demystified"?
Is the audio ai generated now? Sounds a bit different.
I heard some ominous slamming noise in the audio track for this video, are you trapped in the TSMC dungeons? If you dont reply to this comment I will consider you to be under threat and send an extraction team.
Intel is like a sleeping Godzilla that a lot of people hope doesn't wake up they are still as dangerous as a cocked gun!
How timely! Now that Altera went back to independence just couple days ago.
I really like these videos
Is it just me or did ur voice change alot over the last two years :D
If a foundry like intel's or one of the new TSMC foundries is considered out of date, is it just a matter of replacing the lithography machines to use the latest nodes?
SYSTEMS INTEGRATION, TSMC is the expert in that. Intel has low NA EUV litho for soooo long, still don't know how to use them.
You’ve got two options. You keep the fab for that specific node and keep it running as a legacy node, or you re-tool the foundry for the new node. Re-tooling is expensive so only really done if necessary AFAIK
@BellJH yeah I sort of got that, I guess what I meant was, can you just replace the main machines on the floor and continue business as usual, or is it an almost 100% refit?
Now I want a pizza, oh, I meant high performance x86 processors on a leading edge lithography node
Don't something as gate last, was simply that they was lucky? Because from what I remember it wasn't obvious choice.
4:10 sorry, but iPhone don't have Intel, because they decision, not architecture
I think people are really sleeping on not just IFS, but the environment that would lead IFS to be conducive. We are entering an environment that will be increasingly hostile to free trade and outsourcing, and Intel need to take that as a multiplier to competitive capabilities. I feel like many are not seeing it, and when Jensen Huang says that he has yet to visit Trump because "He hasn't received an invitation", I sense the very same complacency that got Intel in the spot it is in today.
You should do a video on Kowloon Walled City
Thanks for talking about me, aka M. calzone, the weirdo 😮😂👏
Something is up with your voice. I hope you are ok. Go try the Baby Boli 8 at Amore Pizza in Gong Guan. It will make you well!
The audio sounds normal at 1.25
1.15 😅
Sounded like Winston Churchill at times. Added some real gravitas.
Get well soon!
The bord earnings request over everything is the main shortcomings
could you make a special of introducing intel leaders and board of directors? I still see this as a bad/dump leadership making, decision, short sighted that cause the whole Once Great Intel FALL.
Damn you for the food analogies. I'm watching this in bed after already brushing my teeth and you are making me hungry. I'll come back tomorrow when I'm less famished.
Hope you get better ASAP, and thanks for another video.