This video shows how to install Quartus 22.1 Lite along with the Questa simulator, including obtaining a free license file. It also shows how to fix two bugs - the first prevents simulations from running while the second bug prevents finite-state machines from being initialised properly. It demonstrates how to perform a simulation and how to upload a design to the DE1-SoC development board.
Recent versions of Quartus disable gate-level simulations by default. The video also shows what configuration option must be changed to enable gate-level simulations.
Simulations not working?
1. Run "lmdiag lmutil" to check the license is correctly installed. (This requires you to have set the environment variable correctly.)
2. Try running Questa directly. If there is a license problem, and you have set the environment variable but haven't rebooted the computer, try rebooting first.
3. If Questa complains about a missing .dll file, then you need to install the Microsoft Visual C++ Redistribution library, from the year 2013 I believe. Try: learn.microsoft.com/en-US/cpp/windows/latest-supported-vc-redist?view=msvc-170#visual-studio-2013-vc-120
4. If you can run Questa directly, but you get an error message when calling it from Quartus before Questa even starts, then the error message (in a dialog box) will tell you the name of a .rpt file you can open to read what the problem is.
00:00 Finding the Quartus download page
00:23 Download page for Quartus 22.1 Lite
01:03 7-zip (for extracting files from tar file)
01:31 Extract files from downloaded Quartus tar file
01:55 Run "setup" from extracted files
03:51 Select "run the quartus prime software" option
04:10 Obtaining a license for Questa simulator
07:30 Move license to appropriate directory
08:14 Set LM_LICENSE_FILE environment variable
09:28 Fix serious bug preventing simulations from running
12:19 Create a Quartus project
13:40 Create our top-level module
14:32 Create our test bench
15:40 Telling Quartus to use our test bench
17:08 Questa window
18:01 Configuration option to allow gate-level simulations
18:44 Fix bug preventing finite-state machines being initialised correctly
19:31 Pin assignments (for DE1-SoC board)
20:15 Programmer tool (for DE1-SoC board)