วีดีโอ

Thank you for your awesome explanation!

thanks for this

Tq!

Will changing the Switching Frequency, i.e Timer Value affect how long the counter will count for. I am having trouble where the counter will count to 255, but still be at 188 and switch duty cycles which causes a high. So it does not finish counting to 255 and resetting.

I think that loops in verilog aren't synthesizable But the generic one bit mux violates my expectations So, what it the state for my design code from synthesbility if I resorted to loops in

For the transmit, I don’t think we need the over sampling. Only the receiver needs the over sampling.

Good tutorial!

Hello Sir, Why did you decide to not have a FIFO in this design?

First time I see the whole process....gold mine😮

Thank you!

Hello Sir, Shouldn't the driver files go into the platform and application files in application project?

Where can I send you my question? Do you have telegram? Please 😢

Hi, I have a question Please I really have problem Can you help me please?

thakyou 🙂

How pixel clock rate and bandwidth are related??

How to calculate pixel clock rate of HDMI

Sir you just earned one lifelong subscriber

thankyou for this

Great videos Anas. What an effort! Are you planning on creating a series on DSP algo on FPGA? Not many tutorials on it.

according to texas instruments documentation at the below link page 24/51 , I think the waveform of operation modes are exchanged www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf?ts=1719455710938

Thanks for such an awesome explanation. I have a question if you can answer. if there is a timing violation and the output goes to the metastable state but do we get the correct output once it comes out of the metastable state or the output can go to either of the logic high or logic low as can be seen the waveform at 4:57?

Baud rate is NOT a term of a UART. They work in bit/second!

excellent. thank you for the videos and playlist

Great video!! only if you can upload the verilog code ...

too helpful u really put a lot of effort into this

Sir, the way you teach is way beyond wht we get to learn in academics, ur videos have essence of partical implementation, which change the way we infer the logic and its implementation in verilog, Thanks for all the resourses that you provided, I wanted to admire your work, thanks for the help.

thanks

Changing D @ the onset of pos edge and it got reflected in Q ; doesn't it violate the hold time condition ? The previous value of D should be reflected @ Q ?

demonstration of "mixing" blocking and non-blocking assignments could be interesting.

Sorry, but I think there is a mistake in the B part. It’s asking about the left side, not the right one, so the answer should be V(left) = -212.77 mV Correct me if I’m wrong please

Thank you and good luck with the channel, you are doing a great job.

Why 16 times we are considering for oversampling

Logic for done in timer ??

why talking like machine gun, difficult to follow

how can I constraint the generated clock?

En los extremos de un solenoide

10:55 The thing I have trouble understanding is how it could have been a combinational circuit even with blocking assignments. Don't the blocking assignments imply registers, and doesn't that also make it sequential? In my mind always_comb should work just like continuous assignments, so I have trouble wrapping my mind around why so many always block constructs (like switches) demand blocking assignments

25 ns for operture is too big. Usually 100 MHz clock is 10ns time period then how even a single flipflop can work

best teacher you can talk till the morming and I can listen without getting bored

Do we have to write the synchronous part in combinational always block? Wouldn't it work like this: always @(negedge clk,negedge reset_n) begin if(!reset_n) Q_reg <= 1'b0; if(!clear_n) Q_reg <= 1'b0; else Q_reg <= Q_next; end

How about a video from wye to delta transformation

thank you

Rather than using if else for 4to1 mux can we use case statement ?

Very useful - Thank you very much for putting it "out there" :)

I have a question at 4:11 Can we still write it as (20-V2) - (V2-V3)/4 - (V2/40) since it's a voltage drop from 20 to v2

Thank you this was really helpful. May I know the resource of the questions?

Hi brother, I got a Friend that needs the whole schematic for the M9. We are in Brazil and it's difficult to find it here. He needs to check some parts to be replaced on one of that. Do you know where on internet can I find it? And if you have it, would you share it?

Thank you so much for your videos

thank you for sharing Sir

whats the use of mealy and moore? where do we use them?