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Explore the way
เข้าร่วมเมื่อ 12 มิ.ย. 2021
Hello budding engineers....
Welcome to Explore the way youtube channel. In this channel, i explore various subjects related to Digital design, VLSI, Microprocessors etc.. I mainly focus on the topics where students feel difficulty. I invite you all to this family where you will learn in easy way.
Please subscribe and become part of this family.
Please keep supporting me with your valuable
LIKES, COMMENTS and SHARES.
For any queries/doubts mail me on:
👉explorethewayofficial@gmail.com
Welcome to Explore the way youtube channel. In this channel, i explore various subjects related to Digital design, VLSI, Microprocessors etc.. I mainly focus on the topics where students feel difficulty. I invite you all to this family where you will learn in easy way.
Please subscribe and become part of this family.
Please keep supporting me with your valuable
LIKES, COMMENTS and SHARES.
For any queries/doubts mail me on:
👉explorethewayofficial@gmail.com
Operation of NMOS Depletion mode transistor || Clear Explanation @ExploretheWAY
In this video, operation of nmos depletion mode transistor is explained.
มุมมอง: 664
วีดีโอ
Design of Half Subtractor using Pass transistor Logic || VLSI Design || Explore the way
มุมมอง 1K9 หลายเดือนก่อน
In this Video, design of Half Subtractor using Pass transistor logic is explained.
Design of Half adder using Pass Transistor Logic || Easy method || Explore the way
มุมมอง 1.6K9 หลายเดือนก่อน
Design of Half adder using Pass Transistor Logic in very easy method.
Sourcing and Sinking Currents in a CMOS device @ExploretheWAY
มุมมอง 1069 หลายเดือนก่อน
In this video, Sourcing and Sinking currents in a CMOS device is explained. #cmos #explain #dica #digital CMOS behavior with Resistive loads Video link: th-cam.com/video/FTW41X1zoYM/w-d-xo.htmlsi=mNMBC8WvVEAZ4K7n
Design of 8 to 1 Multiplexer using pass transistor logic | Clear explanation
มุมมอง 3.4K9 หลายเดือนก่อน
In this video, design of 8 to 1 multiplexer using pass transistor logic is clearly explained. #dica #cmos #passtransistorlogic #8to1multiplexer #vlsidesign #8to1 #8to1mux
CMOS Ex-or gate Queries @ExploretheWAY
มุมมอง 3899 หลายเดือนก่อน
In this video, i discussed the queries asked by subscribers on CMOS Ex-or gate. #cmos #dica #vlsidesign #exor #exorgate #exclusiveorgate #queries #queriessolved
CMOS behavior with Resistive load @ExploretheWAY || Digital IC Applications
มุมมอง 2039 หลายเดือนก่อน
In this video, CMOS behavior with resistive loads is explained. #explain #cmos #dica #CMOS steady state electrical behavior #digital ic applications #exploretheway
CMOS steady state electrical behavior : Logic Levels and Noise margin @ExploretheWAY
มุมมอง 78110 หลายเดือนก่อน
In this video, CMOS steady state electrical behavior : Logic Levels and Noise margin is explained clearly. #explain #cmos #DICA #exploretheway
CMOS OAI gate @ExploretheWAY
มุมมอง 1.3K10 หลายเดือนก่อน
CMOS OR-AND-INVERT GATE @ExploretheWAY #explain CMOS OAI igate
CMOS AND-OR-INVERT(AOI) Gate @ExploretheWAY
มุมมอง 4.1K10 หลายเดือนก่อน
In this video, CMOS implementation of AOI gate is clearly explained.
BiCMOS inverter @ExploretheWAY
มุมมอง 2.8K11 หลายเดือนก่อน
In this video, operation of BiCMOS inverter is explained @ExploretheWAY
Design of NAND GATE and NOR GATE using 2x1 Mux
มุมมอง 4K2 ปีที่แล้ว
Design of NAND GATE and NOR GATE using 2x1 Mux
Design of inverter using various gates @ExploretheWAY
มุมมอง 6632 ปีที่แล้ว
In this video, i explained design of inverter using remaining gates.
Subsystem design:Bus arbitration logic for n-line bus
มุมมอง 4.6K2 ปีที่แล้ว
Subsystem design:Bus arbitration logic for n-line bus is explained.
Implementation of OR GATE using 2x1 Mux
มุมมอง 3.6K2 ปีที่แล้ว
Implementation of OR GATE using 2x1 Mux @ExploretheWAY
Implementation of logic gates using 2x1 Multiplexer @ExploretheWAY
มุมมอง 3.7K2 ปีที่แล้ว
Implementation of logic gates using 2x1 Multiplexer @ExploretheWAY
The NMOS inverter @ExploretheWAY || operation of nmos inverter
มุมมอง 7K2 ปีที่แล้ว
The NMOS inverter @ExploretheWAY || operation of nmos inverter
VHDL CODE FOR T-FLIPFLOP @ExploretheWAY
มุมมอง 2.7K2 ปีที่แล้ว
VHDL CODE FOR T-FLIPFLOP @ExploretheWAY
ElectroStatic Discharge(ESD) @ExploretheWAY
มุมมอง 2.4K2 ปีที่แล้ว
ElectroStatic Discharge(ESD) @ExploretheWAY
VHDL code for EX-OR gate in dataflow style and behavioral style @ExploretheWAY
มุมมอง 9402 ปีที่แล้ว
VHDL code for EX-OR gate in dataflow style and behavioral style @ExploretheWAY
Design of Half adder using VHDL || Dataflow style@ Explore the way
มุมมอง 2.1K2 ปีที่แล้ว
Design of Half adder using VHDL || Dataflow style@ Explore the way
Data flow design elements in VHDL|| Explore the way
มุมมอง 6972 ปีที่แล้ว
Data flow design elements in VHDL|| Explore the way
Latch up in CMOS circuit || Latch up || Explore the way
มุมมอง 13K3 ปีที่แล้ว
Latch up in CMOS circuit || Latch up || Explore the way
Operation of nMOS enhancement mode transistor || Explore the way
มุมมอง 27K3 ปีที่แล้ว
Operation of nMOS enhancement mode transistor || Explore the way
Layout of 2-input CMOS NAND gate || P-WELL process || Explore the way
มุมมอง 17K3 ปีที่แล้ว
Layout of 2-input CMOS NAND gate || P-WELL process || Explore the way
Layout of CMOS INVERTER using P-WELL Process || Explore the way
มุมมอง 13K3 ปีที่แล้ว
Layout of CMOS INVERTER using P-WELL Process || Explore the way
Operation of CMOS INVERTER || Explore the way
มุมมอง 14K3 ปีที่แล้ว
Operation of CMOS INVERTER || Explore the way
Design of 4 to 1 Mux using Pass transistor logic || VLSI DESIGN || Explore the way
มุมมอง 26K3 ปีที่แล้ว
Design of 4 to 1 Mux using Pass transistor logic || VLSI DESIGN || Explore the way
Pretty awesome explaination
very good explanation mam
crystal clear👍
How are you taking the Euler's path??if possible please state some point to keep in mind while taking the Euler's path or if possible just make a video to show how one should take a Euler path while solving questions like these
Thank you ma'am❤
Sum output is incorrect,i have checked the schematic through micro wind software
Great work, Thankyou so much
Thanks
Well explained
yup, it ok, but you have the part draw physical layout in software is gread
the best way to design physical layout from transsitor -level schematic
mam shall we use for mtech mam
Yes you can
Ok thanks mam🎉
Thankyou
Bahut shukriya, you gave me the confidence I need for the final exams
Can we implement the same using PMOS?
Yes, we can
Thanks mam, you just saved me from VLSI exam
Please keep making such videos. It's very useful.
so nice!!!!!! love you!!!!
excellent
Tq
mam in my softwore vdd is not coming how to solve that problem
Add misc library from standard libraries. You can find vdd, gnd in misc library.
Best ❤
Just now I related to pmos and. Nmos states nmos in dot with parallel
excellent explaination tq..
🎉🎉
4+4+4+2+2=16 not 20
Plz watch the video again
why we are consider in sum only taken 1's at 5.59?
But while using this approach, don't we get output in complement form?
one of the best video on 2:1 mux
your truth table is wrong....🐸🐸
That's correct bruuu
Thank you so much ma'am
Good
Good 👍
How can you take Abar and Bbar directly? How can it be interpreted while making a layout out of the given stick diagram
Thank you mam❤
Very good mam 😊 0:12
Thank you!
The way you explained is easily understandable. Thank you 👏
Tqq❤
Take any random Boolean expression and construct the circuit with pass transistor
Thanks mam🎉
Very useful video Thak you ma'am.🎉
Understood mam
Great work mam
how you were take the whole complement of the given boolean expression? i did not understand
Thanks mam❤
+why use inverter in output, ?
The CMOS logic produces complemented function. To get true output, one inverter is required at the output.
This not 30Tr, only 26
Two inverters are used produce s0' and s1'.