วีดีโอ

Good content explained

Sir what about mixed signal jobs?? ..what is the roadmap for it..can you cover the topics for mixed signal job placement..

Superb video sir , till now i thought i was good in these set up and hold time analysis .. but after watching this video , i would say its worth my time because i learnt new appraoches and cleared my misconceptions in this concept ..good job sir , keep going 🔥🔥🔥

please cover effect of jitter and derate in STA

bhaiya verilog course will come in 2025 starting (upto march) or later till oct-nov?? please reply

Hai himanshu, about mixed signal design jobs u didn't say anything in the video. Do we need to prepare analog and digital both for that profile ?

Insightful video.

Great session sir😀

Fpga project on bank vault locker and testing stuck at faults in kogg stone adder are these projects worthy enough to add in resume ??

The Best in the Industry

What do you give suggestions for new GATE ESE Aspirants to get in Mtech,JRF,I tried 2 times ,not successful in GATE 17,18 left it. What will be your tips and tricks for GATE preparation either prev question papers,test series , lectures benifits and finally which is best in your perspective good subject experts in institutes

Thank You Sir! for your guidance, as you mentioned that we need to prepare network theory, control systems, Analog Electronics and Analog IC design but I had a doubt that "is the two playlists of razavi covers both Analog Electronics and Analog IC design?" please reply back sir! I'm waiting for you response. Because why i'm asking this question means "in digital vlsi we have digital electronics separately and digital ic design separately where as in analog vlsi, there is playlists from razavi naming electronics part-1,2.

Again phenomenal video sir as always 😊

loved these contents bhaiya ......want more vlsi oriented vedios please

evela madkondu kelsa engee madtya guruu, super bro neevu

Himanshu , your concept knowledge and teaching is really good. Along with this it would be great for students if you can recommend good books and literature which they can refer.

As know the inductor does not allow a sudden change in the current similarly cap also does not allow a sudden change in voltage so vout going 5v to 0v so voltage is slightly up to compensate the sudden change in voltage similarly happens when vout goes 0v to 5v voltage is slightly down to compensate the sudden change in voltage . I thought this will be another explanation....

Thanku so mucch sir for this tutorial...ur lectures are always so beneficial ❤

How can I contact you bro

Thanks a lot bhai, loved the whole video. I've previously encountered these topics in two of my NPTEL courses where i was able to solve problems but not with this depth and intuition, i used to mess up alot and get confused. This video made my concepts more stronger.

sir, you said that by decreasing vdd vih also deacreses similarly voh also decreases right ?? how there is trade off in noise margin As NMH=VOH-VIH

Correction at 45:55 - The output will be stable at Vdd/2, not predictable. ( Considering kn=kp) Try thinking about PMOS NMOS current. You will understand it

The saviour ❤

Bhaiya aap itne acche videos banate ho...apme dosto ko suggest krne mekn darr lagta hain...kahi unka jyada score na aa jaye tests mein!!😞

Thank you very much for making such informative videos sir. This was a concept I tried so painfully hard to learn. May god bless you❤

Great explaination man.Specially the timing diagrams ,completely understood the logic behind it.

Thank you sir it gonna help a lot

Best on Internet 🔥

Completed the video within one day only!!!Best video till date on yt of sta!! Nvr found all the pattern of questions in one place!!🔥

best video

Very useful and interesting video. Thanks for uploading. 🙏

Sir please provide notes

Hello Himangshu!! Thanks for the video. I have a small doubt. The interviewer asked me the following questions. Can you please explain it once? - why setup and hold time is required? (Necessity) - what happens if setup and hold time are not met?

❤❤❤❤

your content is great but your explanation is not good please focus on explanation power it will help students more

Thank you himanshu sir ❤🎉

Sir, how long will this be public?

❤❤❤

Thank you himanshu sir ❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤️❤️❤️❤️❤️❤️🔥🔥🔥🥺🥺

After bsc can I give gate exam

Congratulations bro😊

At 1:29:12 , you said that when an electron and hole combine , then they will result in forming a -ve ion , but this is not true , they will compensate each other charges and energy will be released in form of heat or light . Rest everything is superbly explained till now 😂

Bhiya calculator hoti h na csir net ma physics k leya