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Learning FPGA Together Part 17: Adders, Subtracters, and Multipliers
17. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/
In this episode we start the 6. lab in the Digital Logic Course. We look at 8-bit accumulator circuit design and its use cases. Then we implement it in VHDL and test in on the DE1-SoC board. An accumulator circuit is an important part of digital logic. For example, it can be used to create DAC wave signal generator or convolution for CNN (neural networks). I hope you enjoy the video and try it yourself :)
-- Watch the following parts live on Twitch www.twitch.tv/bracketscoding
มุมมอง: 164

วีดีโอ

Timing Analysis in Quartus: Learning FPGA Together! TimeQuest Timing Analyzer18:21Timing Analysis in Quartus: Learning FPGA Together! TimeQuest Timing Analyzer
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มุมมอง 6806 หลายเดือนก่อน
16. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ In this episode, we will be going through a tutorial on Digital Logic Simulation and Debugging. We will show you how to set up timing constraints and obtain timing information for a logic circuit using the Quartus Prime Timing Analyzer. To demonstrate thi...
OV7670 Camera + DE10 Standard FPGA: Real-Time Streaming over the Internet1:07OV7670 Camera + DE10 Standard FPGA: Real-Time Streaming over the Internet
OV7670 Camera + DE10 Standard FPGA: Real-Time Streaming over the Internet
มุมมอง 2496 หลายเดือนก่อน
The project displays a video stream from an OV7670 camera module using the DE10-Standard SoC FPGA platform. The video stream is displayed on a VGA port and also processed by an ARM processor of the SoC platform. An Application running on the ARM processor runs a Gstreamer RTSP Server streaming the video via the ethernet interface.
K-MAP implemented with a Multiplexer? HDLBits #7 Karnaugh Map16:48K-MAP implemented with a Multiplexer? HDLBits #7 Karnaugh Map
K-MAP implemented with a Multiplexer? HDLBits #7 Karnaugh Map
มุมมอง 1756 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Learning FPGA Together Part 15: Real-Time Clocks 2/252:23Learning FPGA Together Part 15: Real-Time Clocks 2/2
Learning FPGA Together Part 15: Real-Time Clocks 2/2
มุมมอง 586 หลายเดือนก่อน
15. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ In this episode we finish the 5. lab in the Digital Logic Course. We design a simple finite state machine to display Morse code for 8 letters in the alphabet. The letters are selected by switches and the Morse code is displayed when pressing one of the ke...
Population Count Problem: HDLBits #6 Basic Gates11:02Population Count Problem: HDLBits #6 Basic Gates
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มุมมอง 1046 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Learning FPGA Together Part 14: Real-Time Clocks 1/232:40Learning FPGA Together Part 14: Real-Time Clocks 1/2
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มุมมอง 886 หลายเดือนก่อน
14. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ This episode goes through the 5. lab in the Digital Logic Course. We design modulo-k counter and then use it to create a real time clock with minutes, seconds, and hundredths of a second. The real time clock is displayed on a 7-segment display. Watch the ...
Learning FPGA Together Part 13: Counters 2/237:35Learning FPGA Together Part 13: Counters 2/2
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มุมมอง 426 หลายเดือนก่อน
13. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ This episode goes through the 4. lab in the Digital Logic Course. We start where we left off last time. First, we design a circuit that counts from 0 to 9, and the number is incremented every second. The number is shown on a 7-segment display. Then we alt...
Essential Features in Verilog: HDLBits #5 More Verilog Features14:08Essential Features in Verilog: HDLBits #5 More Verilog Features
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มุมมอง 1766 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Sequential Coding in Circuit Design: HDLBits #4 Procedures15:25Sequential Coding in Circuit Design: HDLBits #4 Procedures
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มุมมอง 1987 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Learning FPGA Together Part 12: Counters 1/226:05Learning FPGA Together Part 12: Counters 1/2
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มุมมอง 1087 หลายเดือนก่อน
12. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ This episode goes through the 4. lab in the Digital Logic Course. We first learn about J-K and T-type Flip-Flops (FF) and then use them to create 6-bit counter. We demonstrate the functionality of the counter by displaying the output on the 7-segment disp...
Mastering Module Hierarchy: HDLBits #3 Modules19:42Mastering Module Hierarchy: HDLBits #3 Modules
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มุมมอง 2777 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Learning FPGA Together Part 11: Latches, Flip-flops and Registers 3/336:15Learning FPGA Together Part 11: Latches, Flip-flops and Registers 3/3
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มุมมอง 1617 หลายเดือนก่อน
11. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ This episode goes through the 3. lab in the Digital Logic Course. We use everything we have learned so far in labs 1, 2 and 3 to finish a bigger project. We save 2 binary numbers in registers, add them together and show the sum on the HEX 7-segment displa...
Combining Signals: HDLBits #2 Vectors10:49Combining Signals: HDLBits #2 Vectors
Combining Signals: HDLBits #2 Vectors
มุมมอง 2067 หลายเดือนก่อน
Welcome to Verilog Practice series, your go-to destination for solutions and walkthroughs of HDLBits challenges! If you're seeking comprehensive guidance on mastering Verilog through practical exercises, you're in the right place! In this series, we explore fundamental concepts in Verilog programming. Join us as we tackle challenges and exercises provided by HDLBits. From basic syntax to more c...
Learning FPGA Together Part 10: Latches, Flip-flops and Registers 2/323:29Learning FPGA Together Part 10: Latches, Flip-flops and Registers 2/3
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มุมมอง 707 หลายเดือนก่อน
10. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/ This episode goes through the 3. lab in the Digital Logic Course. We learn how to implement a D latch and use it to create Master-Slave DFF. We also learn the difference between positive and negative Master-Slave DFF. Finally, we simulate our design using...
Designing Circuits using Code: HDLBits #1 Basics7:09Designing Circuits using Code: HDLBits #1 Basics
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มุมมอง 4607 หลายเดือนก่อน
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Learning FPGA Together Part 9: Latches, Flip-flops and Registers 1/325:40Learning FPGA Together Part 9: Latches, Flip-flops and Registers 1/3
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มุมมอง 817 หลายเดือนก่อน
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Learning FPGA Together! Questa Simulator with Testbenches18:16Learning FPGA Together! Questa Simulator with Testbenches
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Learning FPGA Together Part 7: Numbers and Displays 4/413:58Learning FPGA Together Part 7: Numbers and Displays 4/4
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Learning FPGA Together Part 4: Numbers and Displays 1/438:32Learning FPGA Together Part 4: Numbers and Displays 1/4
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Learning FPGA Together Part 3: Switches, Lights and Multiplexers 2/256:34Learning FPGA Together Part 3: Switches, Lights and Multiplexers 2/2
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Learning FPGA Together! Going through the FPGA Academy Course live!16:49Learning FPGA Together! Going through the FPGA Academy Course live!
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Learning FPGA Together! Going through the FPGA Academy Course live!

ความคิดเห็น

  • @khoiphamang5054
    @khoiphamang5054 หลายเดือนก่อน

    can you share your code, i would love to study your code lovely work

  • @AlienMaxi1817
    @AlienMaxi1817 2 หลายเดือนก่อน

    thank you brother

  • @mirabeauAlberto
    @mirabeauAlberto 2 หลายเดือนก่อน

    Could you pass on your quartus theme, my eyes always suffer when working on FPGA. I would appreciate it very much

  • @andywilliamkamgangnewou6851
    @andywilliamkamgangnewou6851 2 หลายเดือนก่อน

    I just want to ask i tried to implement what you have done but i still have an issue with the programm the accumulator seems not to work properly. i dont know why

  • @andywilliamkamgangnewou6851
    @andywilliamkamgangnewou6851 3 หลายเดือนก่อน

    please can you make a video for the exercise : A simple processor? Thank you a lot for your videos. It is a huge hepl in my study. P

  • @tiny_penguin
    @tiny_penguin 3 หลายเดือนก่อน

    very helpful thanks man!! also ,would you mind mentioning your linkedin?

  • @nmeghana9092
    @nmeghana9092 4 หลายเดือนก่อน

    why tempcarry is declared ? can you plz explain

    • @WhiteBracketsFPGA
      @WhiteBracketsFPGA 4 หลายเดือนก่อน

      In the BCD exercise, I declare a temporary carry to connect the carry-out and carry-in bits of the modules. The top module output carry is just a single bit. Hope this helps!

  • @MsLFilipe
    @MsLFilipe 5 หลายเดือนก่อน

    Excelent video. thank you

  • @hamsterworks
    @hamsterworks 6 หลายเดือนก่อน

    Nice!

  • @newb_embedded040
    @newb_embedded040 6 หลายเดือนก่อน

    which fpga dev board are you using?

    • @WhiteBracketsFPGA
      @WhiteBracketsFPGA 6 หลายเดือนก่อน

      I use the DE1-SoC board. It combines FPGA and ARM processor, which makes it great for all kinds of projects.

  • @WhiteBracketsFPGA
    @WhiteBracketsFPGA 6 หลายเดือนก่อน

    07:36 Even this row can be further simplified :) You can try it on your own.

  • @WhiteBracketsFPGA
    @WhiteBracketsFPGA 7 หลายเดือนก่อน

    Hey guys! I'm going through these exercises fairly quickly to get to the more interesting ones ahead. I will try to explain those in more detail :)

  • @maduk22
    @maduk22 7 หลายเดือนก่อน

    Great tutorial.Thank you!

    • @WhiteBracketsFPGA
      @WhiteBracketsFPGA 7 หลายเดือนก่อน

      Thanks! Glad you liked it :)