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Sir, It's Invigorating. Thankyou 🙂❤

Thank you sir

Hi, thanks for the video. For passive devices there are only ss,ff,tt corner. When we select mosfet in sf and fs corner, which corner should we select for passive devices?

Really heartwarming sir ❤️❤️

This opened my eyes to VLSI research, seriously. I wonder if there was a new architecture for the processors, or maybe the architect in VLSI brought something else, just like Von Neumann and Harvard. Am I still on the right path? Preliminarily, I am into RTL FPGA designing and am still interested in research on these processing and memory circuits, which could also help solve real-time problems. I would love to get connected and discuss my thoughts on ideas I have. Hare Krishna!

Shout out to you sir !!!! Huge Respect 🙏🕺

Can you please tell me that for 64 address lines if I used pre-decoding of 2 x 3to8 decoders using 3input NAND gates and for post decoding used 64 x 2 input NAND gates. Then for calculating number of stages how we will consider branching "B" in that case?

Very comprehensive lectures and a very simple way of teaching..,

Thank you for sharing this content. This was useful.

Excellent explanation sir, i have one query..how metal 1 is patterned for lower nodes using 2 masks Mask A andask B in green and red colors? Is it SADP?

sir if we had greater vth then can we apply a voltage on body with respect to our source to lower done vth because we have freedom to alter vth theoretically in vth general expression. because when we design ckt in cadence then we are using 4 terminal device not 3 the 4th one is of body??

38:27 how did you say the noise margin will be affected

nice explain sir thanks

When will admission for 2025 AY start?

good morning sir, how to get e learning app. pls help regarding analog ic design course

Je ne suis pas ce corps je ne suis Ps ces pe se

Jai maa ❤❤❤ namaste.

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Nice one I am also blessed to hear th-cam.com/video/nxRdOOFGEqQ/w-d-xo.htmlsi=Q5KRxDBU12-IOq04 a Lord Rama stuti in Sanskrit by #prakritisamskriti

send link for e learning app sir

Hi Sir, Related to PROM, Can we Consider this Way...? Like after Testing Memory on the Tester by running Memory BIST... We will get the information Related to Failing Cells... This PROM Stores the information related to Failing Cells and Replacement will happen During Boot Sequence on the Field... Is this Correct? Could you please suggest any Reference Books for Memories... Thanks for your Lectures

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Hello sir, Good afternoon! In the Impact of Varr lowering part: We say the penalty is write time. But isn't writing 0 into the cell faster than before because the pmos now sources lesser current and thus the Vint charge drains faster into the BL? In this case are we saying that write time increases because the '1' write on blti takes a longer time as pmos sources lesser current? Doesn't faster 0 write force PU to switch ON faster and counter this phenomenon?

Hello Sir, Could You please Give an insight of Characterization in any Video ?

(25:12 video point) 1. Sir two flops in same path group would have same skew(if CTS done in such manner). Then the jitter margin would be the same for both? 2. Also,if we want to analyse the path between different flops in different path groups, would they have different jitter margins ?

Thank you for such a bliss!!!🙏🏾

Totally transporting! So Blissful !🙏🏾

Thank you sir, 😊

Hi sir can you recommend any book that i can follow with this course for more understanding.

As a sir's student, I know how good a human being he is as like a teacher he is but never knew about this great work . Respect 🙏

Dear Dr. Please send me Shambhavi sadhna as my mobile changed and all my Sadhguru post gone.I am really frustrated.please do the needful and oblige

Hi sir , can i get ppt of this lecture videos?

Where can I find this program, becouse I have problem with IT.

Thank you sir explaining in detail. My son got EVE in IIIT and we were rating it below ECE. Now understood that both are similar and unique. Purely depends on learner to explore more. Thanks n regards.

Great and informative lectures I went through some of them I am trying to cover more , thanks Anuj sir

Sir i will be joining this year excited to learn from India best teachers

sir at 16:33 when you say, "when I select a word line, 4 words get selected" , so using one mux I select one bit of the 4 2-bit words available at that word line. this implies that using a single mux, for a selected wordline, I can write into 1 bit only (of the 2 bit-word) of the total 8bits in the selected word line, so the folding simply means that I am reducing the word line length for better read and write, and finally using 2 mux I can write only 1 word of the selected word line. so am I correct in concluding that at a time, using 2 mux, I can write into only 2-bits (1 word) of the total 8-bits in a single word line?

you mentioned that the "mux should not be greater than 1 for stability." I am having some difficulty understanding this requirement and would appreciate it if you could elaborate on this point.

Om sri Devi LingaBhyravi namostute 🌹🌺💐❤️🎉ji

how do we decrease RC Delay of a particular wire

32:20 "Line length=64 processor words" are to be accessed (when its a miss, besides fetching 1byte [which takes "Tfirst" time], each access would give 32 bits==4 processor words from SRAM cache memory say L2 to SRAM cache memory L1. hence requires 16 accesses ) but here I may use BURST mode by keeping constant row selected and bursting out 4 processor words in each cycle. Thus, 16 cycles (as we have 16 mux) of each 4 processor words resulting 64 processor words being accessed. but sir you mentioned 4 accesses ? fetch width is the no.of processor words that a memory could send parallely. (1 access = 4 processor words or 1 L2 words) and if that access is a burst mode of 16 cycles will fetch me 64 processor words. Thank you for these valuable lectures sir 😇

Dear Anuj Sir, you are, without a doubt, the best teacher I've ever come across. Your unique ability to make complex topics accessible and engaging is nothing short of remarkable. You don't just teach; you inspire curiosity and a love for learning that extends far beyond the classroom walls.

❤❤❤

🙏🏻

Thanks a lot sir. Awesome course. A must watch for all engineers working in Semiconductor companies

Sir is branch upgradation possible in iiit delhi?

Dual damascene came because we cannot use dry etch on copper

Nice sir 😊

Great, Anuj Sir !!!