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VLSI Classes
เข้าร่วมเมื่อ 16 ต.ค. 2022
10 Virtuoso ADE : Explorer How to select simulator and set simulator options
10 Virtuoso ADE : Explorer How to select simulator and set simulator options
มุมมอง: 128
วีดีโอ
9 Virtuoso ADE Explorer : How to start the Simulation Environment
มุมมอง 1793 หลายเดือนก่อน
9 Virtuoso ADE Explorer : How to start the Simulation Environment
8 Virtuoso ADE Explorer : Analog Simulation Flow
มุมมอง 2543 หลายเดือนก่อน
8 Virtuoso ADE Explorer : Analog Simulation Flow
7 Virtuoso ADE Explorer : How to Switch Between Explorer and Assembler
มุมมอง 313 หลายเดือนก่อน
7 Virtuoso ADE Explorer : How to Switch Between Explorer and Assembler
6 Virtuoso ADE Explorer : What is Outputs Setup, Run Preview, Diagnostics tab and Status Bar
มุมมอง 523 หลายเดือนก่อน
6 Virtuoso ADE Explorer : What is Outputs Setup, Run Preview, Diagnostics tab and Status Bar
5 Virtuoso ADE Explorer : Assistants in ADE Explorer and Schematic Editor
มุมมอง 433 หลายเดือนก่อน
5 Virtuoso ADE Explorer : Assistants in ADE Explorer and Schematic Editor
4 Virtuoso ADE Explorer : Toolbars in ADE Explorer
มุมมอง 503 หลายเดือนก่อน
4 Virtuoso ADE Explorer : Toolbars in ADE Explorer
3 Virtuoso ADE Explorer : Virtuoso ADE Explorer Graphical User Interface
มุมมอง 743 หลายเดือนก่อน
3 Virtuoso ADE Explorer : Virtuoso ADE Explorer Graphical User Interface
2 Virtuoso ADE Explorer : How to Open Virtuoso ADE Explorer
มุมมอง 1173 หลายเดือนก่อน
2 Virtuoso ADE Explorer : How to Open Virtuoso ADE Explorer
1 Virtuoso ADE : Explorer Introducing the maestro cellview
มุมมอง 1123 หลายเดือนก่อน
1 Virtuoso ADE : Explorer Introducing the maestro cellview
27 Razavi Electronics 1, Lec 27, Emitter Followers
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27 Razavi Electronics 1, Lec 27, Emitter Followers
26 Razavi Electronics 1, Lec 26, Common Base Stage
มุมมอง 218 หลายเดือนก่อน
26 Razavi Electronics 1, Lec 26, Common Base Stage
25 Razavi Electronics 1, Lec 25, Biasing Techniques II
มุมมอง 278 หลายเดือนก่อน
25 Razavi Electronics 1, Lec 25, Biasing Techniques II
24 Razavi Electronics 1, Lec 24, Biasing Techniques I
มุมมอง 88 หลายเดือนก่อน
24 Razavi Electronics 1, Lec 24, Biasing Techniques I
23 Razavi Electronics 1, Lec 23, More on Emitter Degeneration
มุมมอง 48 หลายเดือนก่อน
23 Razavi Electronics 1, Lec 23, More on Emitter Degeneration
22 Razavi Electronics 1, Lec 22, Common Emitter Stage with Degeneration
มุมมอง 48 หลายเดือนก่อน
22 Razavi Electronics 1, Lec 22, Common Emitter Stage with Degeneration
21 Razavi Electronics 1, Lec 21, Input & Output Impedances
มุมมอง 128 หลายเดือนก่อน
21 Razavi Electronics 1, Lec 21, Input & Output Impedances
20 Razavi Electronics 1, Lec 20, Common Emitter Stage
มุมมอง 98 หลายเดือนก่อน
20 Razavi Electronics 1, Lec 20, Common Emitter Stage
19 Razavi Electronics 1, Lec 19, Evolution of Ampifiers
มุมมอง 188 หลายเดือนก่อน
19 Razavi Electronics 1, Lec 19, Evolution of Ampifiers
18 Razavi Electronics 1, Lec 18, PNP Transistor
มุมมอง 48 หลายเดือนก่อน
18 Razavi Electronics 1, Lec 18, PNP Transistor
17 Razavi Electronics 1, Lec 17, Bipolar Small Signal Model, Early Effect
มุมมอง 98 หลายเดือนก่อน
17 Razavi Electronics 1, Lec 17, Bipolar Small Signal Model, Early Effect
16 Razavi Electronics 1, Lec 16, Large Signal & Small Signal Operation
มุมมอง 98 หลายเดือนก่อน
16 Razavi Electronics 1, Lec 16, Large Signal & Small Signal Operation
15 Razavi Electronics 1, Lec 15, Transistor Biasing, Transconductance
มุมมอง 168 หลายเดือนก่อน
15 Razavi Electronics 1, Lec 15, Transistor Biasing, Transconductance
14 Razavi Electronics 1, Lec 14, Bipolar Transistor Characteristics, Intro to Biasing
มุมมอง 148 หลายเดือนก่อน
14 Razavi Electronics 1, Lec 14, Bipolar Transistor Characteristics, Intro to Biasing
13 Razavi Electronics 1, Lec 13, Bipolar Transistor Structure & Operation
มุมมอง 408 หลายเดือนก่อน
13 Razavi Electronics 1, Lec 13, Bipolar Transistor Structure & Operation
41 Razavi Electronics 1, Lec 41, Source Followers & Summary
มุมมอง 88 หลายเดือนก่อน
41 Razavi Electronics 1, Lec 41, Source Followers & Summary
40 Razavi Electronics 1, Lec 40, Common Gate Stage
มุมมอง 68 หลายเดือนก่อน
40 Razavi Electronics 1, Lec 40, Common Gate Stage
39 Razavi Electronics 1, Lec 39, Biasing Techniques, Intro to Common Gate Stage
มุมมอง 28 หลายเดือนก่อน
39 Razavi Electronics 1, Lec 39, Biasing Techniques, Intro to Common Gate Stage
38 Razavi Electronics 1, Lec 38, Common Source Stage with Degeneration
มุมมอง 68 หลายเดือนก่อน
38 Razavi Electronics 1, Lec 38, Common Source Stage with Degeneration
37 Razavi Electronics 1, Lec 37, Common Source Variants
มุมมอง 38 หลายเดือนก่อน
37 Razavi Electronics 1, Lec 37, Common Source Variants
How to download in windows... Help me
thank you very much.
nice one
nice explanation all videous
Thanks umashankarreddy Pls like, share & subscribe
Please can you provide any sheet or pdf related to this ?
In which location the run directory is located?
Hi sir I noticed that u have asap7 library. please help me to install the same. I need to simulate finfet based circuits for my project. pls help me with how to simulate finfet. or PLS if you can just provide the cdfFF18nm library it will be very useful. Thank you.
This is invaluable. It is a shame this is such a niche environment, otherwise, this would have had millions of views... Nice to the point, and clear. Thank you.
Is AOI222 comes with which technology
Advanced PDK from cadence (18nm finfet)
These videos are really good can we connect on some social media platform ?
How to fix font size in cadence library?
How to fix font size in cadence library ?
How can I learn more?
Inv_1x 2x etc are based on the cap it can drive right? Why isnt it connected while doing the schematic and where can i find those values?
Yes 1x 2x etc indicates drive strength In schematics, we wont connect capacitor otherwise you will end up getting LVS error for cap. Generally the drive strength is measured in terms of capacitance. If 1x can drive 4 digital gates then 2x can drive twice that of 1x ie 8 digital gates.
@@vlsiclasses oh ok thank you👍
have u ever did Quantus PVS or pegasus run?
Hi Have you ever run Quantus Pvs or Quantus Pegasus for parasitic extractions
Yes I have tried PVS extraction
@@vlsiclasses @vlsiclasses could you please do a video if u can? I used extracted view output and i got an error saying i need some extra files. Then i tried spice output and got .sp file. I made a symbol and tried to do testbench but i get an error when i run the adl simulation. There aren't much demos online, so i was wondering if u can help please?
✅ 'Promo SM'
How is Candace still in business? This is nonsense.
Can I download this virtual machine with this version of Cadence?
Can you pls help me on my project? I need a help on skill language
can i get the project?
These videos are very informative, is there any way I can get the library files to practice
Thank you Pls like, share n subscribe.... To answer ur query, its unfortunately no
*PromoSM* 😉
what about p substrate stamp error ??
Hello, Thank you for your excellent tutorials. I would like to know how did you install PVS and how you got drc_preset file?
You are welcome Please like share & subscribe!!
thankyou bro :)
Please like, share & subscribe!!
good man. Love from Canada. Please make more videos on multi-input and full project on adder
Sure More videos coming soon Please like share and subscribe!!
Very useful brother 🎉 thank you very much
Thank you Please like share & subscribe
Nicely explained , informative video
Please like share & subscribe