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This is an introduction to using the switch inputs and LED outputs on the Altera DE1-SoC FPGA development board. Learn how to select the correct hardware device, write a Verilog module that shows slide and push-button inputs states on the red LEDs and import pin assignments.

What is a minterm? How are minterms formed? How are minterms used?

What is a maxterm? How are maxterms formed? How do we use maxterms?

Learn to translate Boolean logic circuit expressions into Verilog hardware description modules using bitwise operators for AND, OR, NOT. Instantiate and simulate the modules. Use the RTL Views to see the hardware schematic synthesis of the language constructs.

Learn to translate Boolean logic circuit expressions into Verilog hardware description modules using gate primitives such as AND, OR, NOT. Instantiate and simulate the modules. Use the RTL Views to see the hardware schematic synthesis of the language constructs.

Multiple Schematic Files in Project, Add/Remove Files from project, Create/update block symbols, Top Level entity, naming simulations

Learn how to generate a logic gate functional simulation using Quartus Prime Lite software. Set up the project environment. Draw a schematic using not, wire, and, or, and xor gates. Create and configure the simulation settings to produce the functional simulation output.

Module instantiation is often a tricky subject for students learning a hardware description language. It's often easier to understand block schematic diagrams as they provide a visual reference for wiring connections. We create a block schematic solution and then use it to understand how to create the same system with Verilog. The Verilog solution explains using named instantiation to wire (con...

Module instantiation is often a tricky subject for students learning a hardware description language. It's often easier to understand block schematic diagrams as they provide a visual reference for wiring connections. We create a block schematic solution and then use it to understand how to create the same system with Verilog. The Verilog solution explains using named instantiation to wire (con...

After installing Quartus Prime Lite 18.1 software, we verify Windows recognizes the DE1-SoC development board. The demonstration includes creating a Quartus project, writing a Verilog module that uses switches to turn on red LEDs, and the tricks needed to upload the program to the DE1-SoC.

Create a hardware level schematic for the 1Hz clock circuit and program it to an Altera DE2 board. LEDR1 was unexpectedly turning on with the clock signal, simply because I had a second output pin wired to clock[0] as well. The output pin labeled clock[7..0] should be removed, with only a bus wire output connected to the one_hz circuit symbol, named clock[7..0]

Use Quartus II Web Edition software to create a block schematic clock divider circuit. The input reference clock is 50 MHz. Divide by 5 and divide by 10 circuits are used to derive a 1 Hz clock.

Develop the D input state equations and draw the schematic.

Develop D flip flop state equations, draw schematic

Finite State Machine Sequence Detect 110, Excitation Tables

Finite State Machine Sequence Detect 110, part 2

Finite State Machine Sequence Detection, Part 1

D flip flops

D Latch

Seven Segment Display Verilog Case Statements

Seven Segment Display Exercise

Intro to Quartus II Web Edition Simulation

Signed Number Systems, Part 1