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Bhanu Prakash Veldandi
India
เข้าร่วมเมื่อ 17 ธ.ค. 2015
Main theme of this channel : Videos which may help you with concepts or tools that are related to Electrical Engineering.
LNA simulation | Everything from basics | Explains how Mixer loads LNA | Don't miss the end.
This video will help you do the LNA simulations in a right way.
Explains how the loading from mixer has to be included in the simulations.
Explains how the loading from mixer has to be included in the simulations.
มุมมอง: 12 605
วีดีโอ
Cadence Tutorial - 4 | S Parameter analysis | Plotting SP , ZP and ZM
มุมมอง 6K2 ปีที่แล้ว
This video will help you to do SP simulation. Understand the difference between ZP and ZM plots. Will show you the easy way of analysing matching networks.
S and Z Parameters | Understanding the meaning of S & Z parameters and how simulator handles them.
มุมมอง 1.5K2 ปีที่แล้ว
This video will help you understanding S & Z parameters to an extent in detail.
Cadence schematic tutorial - 3 | Handling mosfets | Everything that you must know | Tran & DC sim.
มุมมอง 6222 ปีที่แล้ว
This video covers everything about how to use mosfets in cadence. Topics covered : 1. How to include model file 2. Inverter simulation - Transient simulation 3. Design variables 4. DC simulation and sweeps 5. Id vs VGS
Cadence Schematic tutorial 1 | DC & Transient simulations | Plotting wavefroms.
มุมมอง 7472 ปีที่แล้ว
This video will help you to get started with cadence virtuoso schematic simualtions. Topics covered : Instantiating, editing elements in schematics etc., Bindkeys (short cuts) DC simulation Transient simulation Waveform window.
Cadence Schematic Tutorial - 2 | Transient, AC & HB simulations | waveforms
มุมมอง 1.8K2 ปีที่แล้ว
This video will help you to use several simulations in Cadence Virtuoso Schematics. Topics covered : 1. Adjusting elements and screen in schematic 2. Transient simulation - liberal vs moderate vs conservative 3. Waveforms 4. AC simulation 5. HB simulation
Small signal model of a circuit | Revised | Basics of analog circuits.
มุมมอง 1253 ปีที่แล้ว
In this video, you will understand the notion of small signal model of a circuit or a component, why we are using it and you will be able to justify your calculations or modelling.
How to calculate Looking - in Impedance for any network | Basics of analog circuits.
มุมมอง 3353 ปีที่แล้ว
In this video, you will understand the notion of looking in impedance and how to calculate it without any trouble.
WHAT IS GATE - DRAIN - SOURCE - BULK OF A MOSFET | Basic CMOS Device operation
มุมมอง 1.2K3 ปีที่แล้ว
In this video you will understand the basic MOS device operation, understand the roles of different terminals of a mosfet. You will also understand what is a bulk of a mosfet, what is the basic difference between nmos and pmos. What is a deep n-well. You will understand why the bulk of a nmos goes to ground and bulk of pmos goes to VDD. You will also see the basic layout view of CMOS technology...
How to write a Testbench | Difference between Logical and Bitwise operators | Verilog Part - 3
มุมมอง 2513 ปีที่แล้ว
In this video, You will learn what a Testbench is, How to write a simple testbench, What is a propagation delay, the difference between Logical and Bitwise operators. In this series, you will learn verilog at moderate pace of learning and you will learn to practice it. Verilog ( a HDL ) is an important tool to learn for Digital engineers. By watching this video, you will learn the following top...
User Defined Primitives in Verilog | Learn Verilog in a month, from basics | Part - 2 Contd.
มุมมอง 8043 ปีที่แล้ว
In this video, How to write a verilog module from truth table ( User defined Primitives) is explained in detailed. The difference between Declaration and Instantiation is explained. In this series, you will learn verilog at a moderate pace. Verilog ( a HDL ) is an important tool to learn for Digital engineers. The following topics are covered in this video : 0:00 Intro 0:21 Answers for practice...
How to write verilog module for any combinational circuit | Learn Verilog in a month. Part - 2
มุมมอง 4983 ปีที่แล้ว
In this video, How to write a verilog module for any combinational circuit is explained in detail. The basics like identifiers, keywords and how to write comments are also covered to a full extent. In this series, you will learn verilog at a moderate pace of learning and you will learn to practice it. Verilog ( a HDL ) is an important tool to learn for Digital Engineers. By watching this video,...
What is a Hardware Description Language | Learn Verilog in a month - Starting from basics | part - 1
มุมมอง 8003 ปีที่แล้ว
In this video, When, Where and Why we use a Hardware Description language (HDL) is briefly explained. The history, background details and the purpose of using a HDL is covered. In this series, you will learn verilog at a moderate pace of learning and you will learn to simulate it and practise along with. Verilog ( a HDL ) is an important tool to learn for Digital engineers. By watching this vid...
Hi banu, if it's possible can you put LNA calculation
Thanks sir, I have one doubt I also made differenttial lna but my output signals are in same phase, I checked it many times what could be possible reasons also for some frequency range s21 is negative
Check the inputs of your LNA. Inputs have to be differential.
Hi Bhanu... It would be very helpful if you could make the same detailed video for the PA and I appreciate your good work.
Hello sir Im trying the same LNA circuit for my understanding If you could please tell me every value of the elements in the circuit. Can you please send me screenshot of the design with elements values .. That'll be really helpfull
Hi, I can do that. But understand that W and L change with the process technology and model files. So my design component values may not help you at all.
@@bhanuprakashveldandi893 ok bro tnq
Good morning sir, thank you for this tutorial. I am trying to design an inductorless differential LNA. So far, I have only done the core amplification and haven't done the matching circuit yet. I initially made a single ended LNA and simulated it and got positive s21. When I replicated it and made it into differential LNA, the s21 became negative. I have tried doing the vcvs method and somehow the s21 became consistent at ~-6kdB. Is the mistake on the testbench part or more on the design?
Something wrong with the setup / test bench. You can debug using an AC input and see whether you are getting some gain or not. If you are getting -6kdB S21 that means there is no signal flow. There is no connection between input and output. cadence instead of showing negative infinity, it shows -6kdB kind of values. Also check whether you are giving input properly or not.
sir, can we plot input resistance with respect to time like here you have plotted with respect to frequency
yeah, you can do that. You can measure voltages and currents and use the calculator tool to do V/I operation as a function of time.
goo morning sir,i want some guidance regarding cadence tool sir
Hi, what guidance you need ?
sir can you explain the design of the struture to obtain the component values
sorry for the delayed response, but I would drop a video soon. I have taken a long break from youtube. I will be back at it.
Hello sir Im trying the same LNA circuit for my understanding If you could please tell me every value of the elements in the circuit. Can you please send me screenshot of the design with elements values .. That'll be really helpful for me. Thank you 😊
My component values may not help you if the technology file (model file) is different.
Thank you very much for the detailed video! I am still a little confused on how to measure the gate capacitance of the mixer. Since you mentioned we need this to get rid of loading effect at the LNA output. Please kindly elaborate, thanks
Put port. Use SP analysis and see looking in impedance and back calculate the capacitance from the imaginary part of impedance.
How to calculate power dissipation for this circuit
Power dissipation is nothing but total voltage across the circuit x total current drawn or pumped into the circuit. So it's just VDD x Idc. Where Idc is the DC current drawn and VDD, 0 are the power supplies.
keep up the good work <3
Awesone brother this was really helpful a whole hearted thanks from my side. Hope you will get a better reach in future for your hard work
Thanks man.
If possible do different techniques of simulation for LNA using Cadence also simulation for learning power consumption could be more helpful keep it up brother waiting for more Low Noise Amplifier videos for wide band frequencies like 5GHz, 6GHz
@@Hostile92YT yeah. Will try to different methods of simulation. The simulation procedure is same for UWB or at any frequency. With regards to power consumption, it's VDD x DC current (if you have differential LNA). If it's single ended, you will get ac power consumption also. In differential, ac power cancels out.
@@bhanuprakashveldandi893 Brother please explain the Transistor parameters (width, length, fingers) you have used in this video for me using a 90nm nmos transistor I couldn't achieve better results, infact the results are disastrous the gain is going negative and Noise figure is going into hundreds of dB when I am using the nmos transistor from gpdk090. Please help me with this issue brother
Its not only dependent on the transistor parameters. Its dependent on the matching network. If your S11 is bad, your S21 is automatically bad. If your load is not at resosnance, you will get bad gain and NF. Try doing a common source LNA, where there is Inductor at the source and gate of the mosfet. Use a cascode stage, if required and Check if your load is resonating at required freq. of operation.
Just one caution : you have to zero out the independent source at the input ( source used for excitation at the input side ) when you are calculating Zout or Z looking in from output side.
Biceps 🙏
Feeling blessed after getting a comment from the legend.
Hopefully part 1 of a multipart series!! :)
You want me to continue this and make a series? Will try. 😅
Good explanation 👌
First :p
Second :P
masssssssssssss
massssssssss
Nice 🔥
Thanks 🔥
Drop your doubts in the comments section. Please ignore the first 2secs editing screen. Next video will be there in 3 - 4 days. At 10:50 ( writing module with boolean expressions ) - you don't have to use the wire keyword. I have forgot to delete that statement.
Drop your doubts in the comments section. I have tried to give you a brief explanation. More details will be covered in later videos.