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TechSimplified TV
India
เข้าร่วมเมื่อ 25 ธ.ค. 2019
Mission : Build a Knowledge Bridge Between Academics & VLSI/Semiconductor(Si) Industry !
We provide Self Learning Free VLSI Courses for the people looking for free alternatives to proprietary and paid VLSI Courses.
Use Playlist Page To Find The Complete Courses.
Audience : Fresher/Graduate/Masters in Microelectronics/Electronics/VLSI.
Emails :
Business : business@techsimplifiedtv.in
Tech Query : connect@techsimplifiedtv.in
Founder / Co-Editor : Mridul Sengupta [ Worked In/For VLSI Companies/Grade : Invecas (Technical Lead ), Synopsys , TexasInstruments , STMicroelectronics , InterraSystems ]
Manager / Co-Editor : Munmun Dey [ Worked In/For VLSI Companies : Intel (Module Lead) , Synapse-Design , Synopsys, TexasInstruments , InterraSystems ] . Achievement Award : University Topper / Gold Medallist .
Notice & Legal : www.techsimplifiedtv.in/p/terms-and-conditions.html
Courtesy : Bensound.com , Pixabay.com, Pexels.com & Topfreeintro.com
We provide Self Learning Free VLSI Courses for the people looking for free alternatives to proprietary and paid VLSI Courses.
Use Playlist Page To Find The Complete Courses.
Audience : Fresher/Graduate/Masters in Microelectronics/Electronics/VLSI.
Emails :
Business : business@techsimplifiedtv.in
Tech Query : connect@techsimplifiedtv.in
Founder / Co-Editor : Mridul Sengupta [ Worked In/For VLSI Companies/Grade : Invecas (Technical Lead ), Synopsys , TexasInstruments , STMicroelectronics , InterraSystems ]
Manager / Co-Editor : Munmun Dey [ Worked In/For VLSI Companies : Intel (Module Lead) , Synapse-Design , Synopsys, TexasInstruments , InterraSystems ] . Achievement Award : University Topper / Gold Medallist .
Notice & Legal : www.techsimplifiedtv.in/p/terms-and-conditions.html
Courtesy : Bensound.com , Pixabay.com, Pexels.com & Topfreeintro.com
What is Placement in VLSI Physical Design?
This video provides a comprehensive discussion on various aspects of placement in VLSI physical design, an essential step in the design flow. We begin by outlining the overall design flow and delve into the objectives and challenges associated with the placement process. The video explores different types of placement techniques, including global placement and optimization strategies, to achieve efficient designs. It also covers advanced methods like min-cut placement, analytic placement, and simulated annealing, explained across multiple detailed segments. Furthermore, modern placement strategies are highlighted, followed by an in-depth explanation of the critical steps of legalization and detailed placement to ensure design correctness and compliance.
Read This As Text @
Chapters for easy navigation:
00:00 Beginning & Intro
00:33 Chapter Index
01:22 Design Flow & Placement
04:13 Objective & Challenges of Placement
06:46 Different Types of Placement
08:00 Optimization in Placement - I
10:56 Optimization in Placement - II
13:38 Modern Placement- I
17:08 Modern Placement- II
20:03 Min-cut Placement -I
22:34 Min-cut Placement -II
25:57 Analytic Placement - I
28:19 Analytic Placement - II
31:46 Simulated Annealing - I
33:31 Simulated Annealing - II
35:02 Global Placement
36:68 Legalization - I
38:48 Legalization - II
40:13 Detailed Placement -I
41:49 Detailed Placement -II
#vlsidesign
#physicaldesign
#vlsitraining
Courtesy:
Sound by : TH-cam Music & Bensound.com
Video by imotivation from Pixabay
Image by Jorge Guillen from Pixabay
Image by robtowne0 from Pixabay
Image by Robin Higgins from Pixabay
Image by Samuel Faber from Pixabay
Photo by Tim Gouw from Pexels
Photo by Dom J from Pexels
Image by pngegg.com
Image by testandmeasurement.com
Image by Ferenc Keresi from Pixabay
This video suggests:
"comprehensive discussion on VLSI placement in physical design"
"placement techniques in VLSI design flow"
"global placement and optimization strategies in VLSI"
"advanced methods for VLSI placement design"
"min-cut placement technique in VLSI design"
"analytic placement in VLSI physical design"
"simulated annealing for VLSI placement optimization"
"modern placement strategies for VLSI design"
"legalization and detailed placement in VLSI"
"challenges in VLSI physical design placement process"
"achieving efficient designs with VLSI placement techniques"
"objectives and challenges in VLSI placement"
"critical steps in VLSI placement legalization and detailed placement"
"optimization strategies for VLSI global placement"
"detailed explanation of VLSI placement techniques and strategies"
Read This As Text @
Chapters for easy navigation:
00:00 Beginning & Intro
00:33 Chapter Index
01:22 Design Flow & Placement
04:13 Objective & Challenges of Placement
06:46 Different Types of Placement
08:00 Optimization in Placement - I
10:56 Optimization in Placement - II
13:38 Modern Placement- I
17:08 Modern Placement- II
20:03 Min-cut Placement -I
22:34 Min-cut Placement -II
25:57 Analytic Placement - I
28:19 Analytic Placement - II
31:46 Simulated Annealing - I
33:31 Simulated Annealing - II
35:02 Global Placement
36:68 Legalization - I
38:48 Legalization - II
40:13 Detailed Placement -I
41:49 Detailed Placement -II
#vlsidesign
#physicaldesign
#vlsitraining
Courtesy:
Sound by : TH-cam Music & Bensound.com
Video by imotivation from Pixabay
Image by Jorge Guillen from Pixabay
Image by robtowne0 from Pixabay
Image by Robin Higgins from Pixabay
Image by Samuel Faber from Pixabay
Photo by Tim Gouw from Pexels
Photo by Dom J from Pexels
Image by pngegg.com
Image by testandmeasurement.com
Image by Ferenc Keresi from Pixabay
This video suggests:
"comprehensive discussion on VLSI placement in physical design"
"placement techniques in VLSI design flow"
"global placement and optimization strategies in VLSI"
"advanced methods for VLSI placement design"
"min-cut placement technique in VLSI design"
"analytic placement in VLSI physical design"
"simulated annealing for VLSI placement optimization"
"modern placement strategies for VLSI design"
"legalization and detailed placement in VLSI"
"challenges in VLSI physical design placement process"
"achieving efficient designs with VLSI placement techniques"
"objectives and challenges in VLSI placement"
"critical steps in VLSI placement legalization and detailed placement"
"optimization strategies for VLSI global placement"
"detailed explanation of VLSI placement techniques and strategies"
มุมมอง: 0
วีดีโอ
LTSpice (v24): CMOS NAND using Monolithic MOSFETs | Response by Transient Analysis
มุมมอง 2
Discover how to construct a CMOS NAND gate using four monolithic PMOSFETs and NMOSFETs in this tutorial! Learn why the PMOSFETs are designed with double the area of NMOSFETs for mobility balancing, and see how pulsed square waveforms with varying ON and OFF times are used as inputs to match the NAND gate truth table. We’ll also demonstrate proper DC biasing and transient analysis to evaluate th...
LTSpice (v24): FullWave Rectifier Circuit Using Diode 1N4007 | Response by Transient Analysis
มุมมอง 1449 ชั่วโมงที่ผ่านมา
In this video, we delve into the construction of a full-wave rectifier circuit using the 1N4007 diode, tackling the unique challenge of working without a transformer in LTSpice. To overcome this limitation, we employ an equivalent circuit design that incorporates two voltage-controlled voltage sources (VCVS), a concept thoroughly explained in our earlier theoretical episodes. The input for the ...
Layout vs. Schematic in VLSI Physical Design using NETGEN - Ep: 3
มุมมอง 1
In this video, we walk through three practical examples using NETGEN to tackle common Layout versus Schematic (LVS) issues in VLSI design. We start with a simple introduction to the topic and provide a clear chapter index for easy navigation. After explaining a buffer circuit, we use it in our examples. We also compare SPICE files to highlight why LVS tools are essential. By exploring common pr...
LTSpice (v24): CMOS Inverter using Monolithic MOSFETs | Response by Transient Analysis
Learn how to design and analyze a CMOS inverter in this detailed tutorial! We demonstrate the construction of a CMOS inverter using PMOS and NMOS transistors, with the PMOS having double the area of the NMOS for optimal mobility balancing of major and minority carriers. Explore the use of a square wave input, proper DC biasing, and transient analysis to evaluate the performance and functionalit...
LTSpice (v24): Diode & Zener Circuits | Transient & DC Sweep Analysis
มุมมอง 226วันที่ผ่านมา
In this video, we delve into several key topics related to circuit simulation and analysis using LTSPICE. We begin by drawing schematics and simulating circuits with fundamental active elements like the PN junction diode and Zener diode. Specifically, we examine the characteristics of the 1N914 diode through DC and temperature sweeps to understand its behavior under varying conditions. Next, we...
VLSI Design Demystified: How Microchips Are Designed and Built | TSA Podcast
มุมมอง 12814 วันที่ผ่านมา
Welcome to the TSA Podcast! In this episode, we take you on a fascinating journey into the world of microchip creation, focusing on VLSI (Very Large Scale Integration). Learn about the intricate stages of VLSI design, from managing power, timing, and signal integrity to the pivotal roles of design companies, EDA tools, and semiconductor foundries. Discover how front-end and back-end design shap...
Exploring R-L-C Series Circuits: Sine, PWL & AC Sources | Transient (.TRAN) & AC (.AC) Analysis
มุมมอง 28714 วันที่ผ่านมา
In this video, we explored several key concepts and practical applications using LTSpice. We began by creating an LCR series circuit using the schematic editor, laying the groundwork for the experiments that followed. First, we conducted transient analyses by applying different input voltages-starting with a sine wave and then transitioning to a PWL (Piecewise Linear) input voltage-to observe a...
LTSpice (v24): GUI & Toolbox Basics Tutorial for VLSI Analog Design & Verification Enthusiasts
มุมมอง 13721 วันที่ผ่านมา
In this video, we dive into several key topics essential for any VLSI enthusiast, starting with a detailed overview of the basic GUI interface and toolbox features in LTSpice. 🎨 User Interface and Toolbox Basics Learn the fundamentals of LTSpice's GUI, designed specifically for VLSI enthusiasts. Get comfortable with the layout and discover how to efficiently navigate through the toolbox. 📚 Buil...
Essential Guide to Verification IP (VIP): Strategies, Flow Chart, and Advantages Explained
มุมมอง 218หลายเดือนก่อน
In this video, we delve into key aspects of verification, beginning with an overview of general verification strategies that are essential for ensuring reliable design and functionality. We explore the need for robust verification processes, emphasizing their role in enhancing design accuracy and reliability, especially in complex systems. A detailed verification flow chart is presented to guid...
VLSI Synthesis: Complete Guide from Basics to Advanced | Theory & Hands-On Practical Marathon
มุมมอง 387หลายเดือนก่อน
This video marathon covers key concepts in VLSI synthesis. It begins with an introduction to synthesis, the V-Curve of VLSI design, abstraction levels, and the Y-Diagram, explaining the coexistence of domains and differences between HDL and synthesis compilers. It further explores the importance of abstraction in VLSI and the synthesis process, including pre-synthesis checks, standard cell libr...
Layout vs. Schematic in VLSI Physical Design using NETGEN - Ep: 2
มุมมอง 164หลายเดือนก่อน
Layout vs. Schematic in VLSI Physical Design using NETGEN - Ep: 2
Layout vs. Schematic in VLSI Physical Design using NETGEN - Ep:1
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Layout vs. Schematic in VLSI Physical Design using NETGEN - Ep:1
Downloading and Installing LTSpice (v24) on Windows 10
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Downloading and Installing LTSpice (v24) on Windows 10
How to Install and Use Tclint: The Ultimate Tcl Linting Tool
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How to Install and Use Tclint: The Ultimate Tcl Linting Tool
Standard Cell Marathon : Key Concepts, Classifications, Design and Characterization
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Pin Assignment and Power-Ground Routing in Physical Design
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Pin Assignment and Power-Ground Routing in Physical Design
Comprehensive Guide to NOISE, DISTORTION, and SENSITIVITY Sim Sweep Control & Analysis in SPICE
มุมมอง 1062 หลายเดือนก่อน
Comprehensive Guide to NOISE, DISTORTION, and SENSITIVITY Sim Sweep Control & Analysis in SPICE
Comprehensive Guide to AC, DC, and Transient Simulation Sweep Control & Analysis in SPICE
มุมมอง 973 หลายเดือนก่อน
Comprehensive Guide to AC, DC, and Transient Simulation Sweep Control & Analysis in SPICE
AI and IoT: The Power Duo Shaping Our Future! 🌐🤖
มุมมอง 483 หลายเดือนก่อน
AI and IoT: The Power Duo Shaping Our Future! 🌐🤖
Complete Python 3 Guide for VLSI Automation | In-Depth Marathon Tutorial Episode
มุมมอง 7843 หลายเดือนก่อน
Complete Python 3 Guide for VLSI Automation | In-Depth Marathon Tutorial Episode
How IoT and Tiny Chips Revolutionized Our World | The Evolution of Smart Technology
มุมมอง 743 หลายเดือนก่อน
How IoT and Tiny Chips Revolutionized Our World | The Evolution of Smart Technology
Floorplanning in VLSI Physical Design
มุมมอง 6343 หลายเดือนก่อน
Floorplanning in VLSI Physical Design
From Analog to DAB+ : The Evolution and Future of Radio Technology
มุมมอง 1203 หลายเดือนก่อน
From Analog to DAB : The Evolution and Future of Radio Technology
How to Simulate an Dependent Power Source in SPICE: Step-by-Step Guide
มุมมอง 843 หลายเดือนก่อน
How to Simulate an Dependent Power Source in SPICE: Step-by-Step Guide
How to Simulate an Independent Power Source in SPICE: Step-by-Step Guide
มุมมอง 734 หลายเดือนก่อน
How to Simulate an Independent Power Source in SPICE: Step-by-Step Guide
Verilog VLSI Tutorial: Comprehensive Guide from Beginner to Advanced - Marathon Episode
มุมมอง 5334 หลายเดือนก่อน
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Mastering Electrical Characterization with SPICE: Essential Techniques for VLSI Applications
มุมมอง 1124 หลายเดือนก่อน
Mastering Electrical Characterization with SPICE: Essential Techniques for VLSI Applications
Partitioning in VLSI Physical Design & Technology
มุมมอง 6134 หลายเดือนก่อน
Partitioning in VLSI Physical Design & Technology
Mastering Simulation Iterations in SPICE: A Guide to ALTER Philosophy and Parameters
มุมมอง 1124 หลายเดือนก่อน
Mastering Simulation Iterations in SPICE: A Guide to ALTER Philosophy and Parameters
Any reason why the FEOL plot is not: A) a rectangle: why does SF corner have a slightly faster NMOS than SS and a slightly slower PMOS than FF? B) a square: why is F of NMOS faster than F of PMOS? I will appreciate you addressing these queries. Thanks!
Will plan some QnA/FAQ episode based on your questions !
@@TechSimplifiedTV sure, thanks so much! If possible, you may please explain very briefly here, maybe in just a few lines; otherwise, I will wait for your QnA/FAQ upload, hopefully very soon.
good knowledge
You're welcome 😊 ! It seems The Videos Helped You ! Please share this channel in your known or professional circle to spread the help to other also !
what about the leakage of transistor M2 shown in slide at time stamp 31:25
what is the meaning of ON resistance ? ON resistance of NMOS and PMOS
Never forget it is semi-conductor not a conductor. That is why it has resistance in on time also. Rest of the explanation for your help. =================================================================== ON Resistance in CMOS and Its Significance : What is ON Resistance? ON resistance is the effective resistance a MOS transistor (NMOS or PMOS) offers when it is fully turned on and operating in the linear (ohmic) region. It is a key parameter that affects the power dissipation, speed, and overall performance of circuits using MOSFETs. ON Resistance of NMOS and PMOS 1. NMOS ON Resistance: When an NMOS transistor is turned on, its ON resistance depends on factors such as the electron mobility, the width-to-length ratio of the transistor (W/L), the gate voltage above the threshold, and the oxide capacitance. NMOS devices generally have lower ON resistance compared to PMOS devices due to the higher mobility of electrons. 2. PMOS ON Resistance: When a PMOS transistor is turned on, its ON resistance is determined by similar factors as NMOS, but the lower mobility of holes results in higher ON resistance. To compensate, PMOS transistors are typically designed wider than NMOS transistors to balance performance in CMOS circuits. Significance of ON Resistance in CMOS 1. Power Dissipation: - Dynamic Power Dissipation: Lower ON resistance reduces resistive power losses during transistor switching, improving circuit efficiency. - Static Power Dissipation: Although static power is low in CMOS circuits, lower ON resistance can minimize power loss during leakage scenarios. 2. Signal Propagation Delay: - The switching speed of a CMOS circuit is influenced by ON resistance. Lower ON resistance results in faster charging and discharging of load capacitances, reducing delays and enhancing performance. 3. Voltage Swing and Noise Margins: - High ON resistance can lead to incomplete switching of the transistors, reducing the voltage swing at the output. This degrades noise margins and may cause logic errors, especially in high-speed circuits. 4. Power Supply Voltage Scaling: - In modern CMOS designs, power supply voltages are scaled down to reduce power consumption. Lower supply voltages reduce the driving capability of transistors, which increases ON resistance. Designers mitigate this by optimizing the size and aspect ratios of transistors. 5. Energy Efficiency in Low-Power Design: - Lower ON resistance minimizes energy losses during switching, which is especially crucial in low-power CMOS designs used in applications like IoT and portable devices. 6. Symmetry and Balancing in CMOS: - CMOS circuits rely on the complementary operation of NMOS and PMOS transistors. The PMOS transistor typically has higher ON resistance, which can create imbalances in switching characteristics. Designers adjust transistor dimensions to achieve balanced rise and fall times and maintain efficient operation. 7. Thermal Effects: - High ON resistance can cause localized heating in transistors due to resistive losses. This can degrade reliability and performance, particularly in high-power or densely packed CMOS circuits. Factors Affecting ON Resistance: - Transistor Dimensions (W/L): Increasing the width-to-length ratio reduces ON resistance. - Gate Voltage: Higher gate voltage relative to the threshold voltage reduces ON resistance. - Mobility: NMOS devices have lower ON resistance than PMOS due to higher electron mobility. - Temperature: Higher temperatures reduce mobility, leading to increased ON resistance. Conclusion: ON resistance in CMOS circuits plays a crucial role in determining performance, power efficiency, and reliability. By minimizing ON resistance through careful design and optimization, CMOS circuits achieve faster operation, lower power dissipation, and improved functionality, making them suitable for a wide range of modern electronic applications.
Sir as a Masters student in VLSI, which all scripting language should i study for placement purposes in India
Answer is here : th-cam.com/video/gOoxLQGXq5U/w-d-xo.html
Contact Kunal Ghosh for Internship and/or Sqadron Board : Mob no. 9686428727 Email - kunalpghosh@gmail.com
1:14:00 can I know more details about it sir?
You can contact Kunal : Mob no. 9686428727 Email - kunalpghosh@gmail.com
Kunal ghosh sir 😯i have done internship in his vsdsquadron
Full Episode : th-cam.com/users/liveDYOCMlzdu7A?feature=share
Good class
You're welcome 😊 ! It seems The Videos Helped You ! Please share this channel in your known or professional circle to spread the help to other also !
What can i use company name if im student
Your University/College/Institution Name !
You're welcome 😊 ! It seems The Videos Helped You ! Please share this channel in your known or professional circle to spread the help to other also !
I'm currently using Ubuntu 20.04 version , the installation is stuck at final processing, downloading 2024.1 package could you please help ?
It seems the server connection lost.Be sure to be connected through LAN. Restart the process again.
OMG 🌝
You're welcome 😊 ! It seems The Videos Helped You ! Please share this channel in your known or professional circle to spread the help to other also !
Excellent video!! Keep them coming!👏👏
You're welcome 😊 ! It seems The Videos Helped You ! Please share this channel in your known or professional circle to spread the help to other also !
at 19:05, I got this (my yosys 0.33 ) yosys> dfflibmap -liberty cmos_cells.lib 5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. cell DFFSR (noninv, pins=5, area=18.00) is a direct match for cell type $_DFFSR_PPP_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ \DFFSR _DFFSR_PPP_ (.C( C), .D( D), .Q( Q), .R( R), .S( S)); 5.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\counter': mapped 3 $_DFF_P_ cells to \DFF cells.
Delete the testcase, Freshly Download The Testcase Again, run from beginning.
Verilog (Digital) Marathon : th-cam.com/video/ZVtGTEBd30M/w-d-xo.html Verilog (Analog) Marathon : th-cam.com/video/imEeLptoipM/w-d-xo.html TCL Marathon : th-cam.com/video/v8eu-CCrm-E/w-d-xo.html Linux & Shell Scripting Marathon : th-cam.com/video/iv2at90nr74/w-d-xo.html PERL Marathon : th-cam.com/video/iJxsFJR3vHk/w-d-xo.html UPF Marathon : th-cam.com/video/ocFfLt8wbjs/w-d-xo.html VLSI FRESHER ROADMAP Marathon : th-cam.com/video/5pxaFYjT750/w-d-xo.html STA Marathon (THEORY) : th-cam.com/video/dOdV6OvCQTY/w-d-xo.html STA Marathon (I/O FILES) : th-cam.com/video/_6fX7T1d4qs/w-d-xo.html STA Marathon (BONUS) : th-cam.com/video/gz_NldlaibQ/w-d-xo.html STA Marathon (PRACTICAL WITH OPEN-TIMER) : th-cam.com/video/DogAWB-Ym2s/w-d-xo.html ELECTROMIGRATION(EM) & IR-ROP Marathon : th-cam.com/video/y6dt9vv4KrI/w-d-xo.html
Verilog (Digital) Marathon : th-cam.com/video/ZVtGTEBd30M/w-d-xo.html Verilog (Analog) Marathon : th-cam.com/video/imEeLptoipM/w-d-xo.html TCL Marathon : th-cam.com/video/v8eu-CCrm-E/w-d-xo.html Linux & Shell Scripting Marathon : th-cam.com/video/iv2at90nr74/w-d-xo.html PERL Marathon : th-cam.com/video/iJxsFJR3vHk/w-d-xo.html UPF Marathon : th-cam.com/video/ocFfLt8wbjs/w-d-xo.html VLSI FRESHER ROADMAP Marathon : th-cam.com/video/5pxaFYjT750/w-d-xo.html STA Marathon (THEORY) : th-cam.com/video/dOdV6OvCQTY/w-d-xo.html STA Marathon (I/O FILES) : th-cam.com/video/_6fX7T1d4qs/w-d-xo.html STA Marathon (BONUS) : th-cam.com/video/gz_NldlaibQ/w-d-xo.html STA Marathon (PRACTICAL WITH OPEN-TIMER) : th-cam.com/video/DogAWB-Ym2s/w-d-xo.html ELECTROMIGRATION(EM) & IR-ROP Marathon : th-cam.com/video/y6dt9vv4KrI/w-d-xo.html
Verilog (Digital) Marathon : th-cam.com/video/ZVtGTEBd30M/w-d-xo.html Verilog (Analog) Marathon : th-cam.com/video/imEeLptoipM/w-d-xo.html TCL Marathon : th-cam.com/video/v8eu-CCrm-E/w-d-xo.html Linux & Shell Scripting Marathon : th-cam.com/video/iv2at90nr74/w-d-xo.html PERL Marathon : th-cam.com/video/iJxsFJR3vHk/w-d-xo.html UPF Marathon : th-cam.com/video/ocFfLt8wbjs/w-d-xo.html VLSI FRESHER ROADMAP Marathon : th-cam.com/video/5pxaFYjT750/w-d-xo.html STA Marathon (THEORY) : th-cam.com/video/dOdV6OvCQTY/w-d-xo.html STA Marathon (I/O FILES) : th-cam.com/video/_6fX7T1d4qs/w-d-xo.html STA Marathon (BONUS) : th-cam.com/video/gz_NldlaibQ/w-d-xo.html STA Marathon (PRACTICAL WITH OPEN-TIMER) : th-cam.com/video/DogAWB-Ym2s/w-d-xo.html ELECTROMIGRATION(EM) & IR-ROP Marathon : th-cam.com/video/y6dt9vv4KrI/w-d-xo.html
Verilog (Digital) Marathon : th-cam.com/video/ZVtGTEBd30M/w-d-xo.html Verilog (Analog) Marathon : th-cam.com/video/imEeLptoipM/w-d-xo.html TCL Marathon : th-cam.com/video/v8eu-CCrm-E/w-d-xo.html Linux & Shell Scripting Marathon : th-cam.com/video/iv2at90nr74/w-d-xo.html PERL Marathon : th-cam.com/video/iJxsFJR3vHk/w-d-xo.html UPF Marathon : th-cam.com/video/ocFfLt8wbjs/w-d-xo.html VLSI FRESHER ROADMAP Marathon : th-cam.com/video/5pxaFYjT750/w-d-xo.html STA Marathon (THEORY) : th-cam.com/video/dOdV6OvCQTY/w-d-xo.html STA Marathon (I/O FILES) : th-cam.com/video/_6fX7T1d4qs/w-d-xo.html STA Marathon (BONUS) : th-cam.com/video/gz_NldlaibQ/w-d-xo.html STA Marathon (PRACTICAL WITH OPEN-TIMER) : th-cam.com/video/DogAWB-Ym2s/w-d-xo.html ELECTROMIGRATION(EM) & IR-ROP Marathon : th-cam.com/video/y6dt9vv4KrI/w-d-xo.html
I have doubt regarding UVC and VIP haw both are connected or something else ?
UVC (Universal Verification Methodology Verification Component) and VIP (Verification IP) are both connected in the context of digital design verification. UVC is a modular component in UVM used to verify specific design aspects (like components, interfaces, or protocols) through defined classes and methods. VIP refers to reusable verification solutions, often built using UVCs, to verify protocols or interfaces in a broader sense. In essence, UVCs are the building blocks for creating VIPs. They are interconnected, with VIPs leveraging UVCs to implement protocol verification in digital designs.
Sir, I think the diode placement towards gnd is not correct plz once recheck it.
We will check !
in first slide (why is it "leaves is => green" executed first)
Add couple of more key & value pairs (different from existing) in the code . Choose keys starting alphabetically lower and higher values. Then run the code to see which one is executed first . You will get the explanation by yourself.
Proud of U Alok...👍❤️
Thank you so much
How to save the waveform
The detailing is covered here : th-cam.com/video/ZVtGTEBd30M/w-d-xo.html
Hi, Can you make a video on vim editor? It will be very helpful.
It is stops in the final processing sir,how to rectify it sir?
Raise Your Voice at Xilinx Support : support.xilinx.com/s/topic/0TO2E000000YKXwWAO/installation-and-licensing?language=en_US
Its a typical software issue , you can ask/search for the solution in Xilinx Forum Here : support.xilinx.com/s/topiccatalog?language=en_US
By just adding a timing diagram to each constraint, to show what it does, would be a great assistance.... just talking about it could have multiple interpretations....
How to Download GPDK - 180nm PDK
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Need Separate video on Library Characterization. Please 🙏
I'm very thankful for your valuable information.
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@@TechSimplifiedTV Sure, I've one doubt actually pre simulations every corner is giving good results, but after post simulations SS40 and SS -40 are failing, and rest of them where coming good what might be the reason for this....? .
The problem you are mentioning here , there could be two ways to approach: 1. Check with your senior/manager who are more experienced than you whether they have faced similar issues , if so you will get the solution within your team or you might have a Known Problem & Solution Repository within your company - check there. 2. You can open/raise a ticket. all EDA vendors have strong team of application engineers and they are very efficiently trained to solve customer issues. They are the right persons to help you with the tool specific query. Thanks for approaching.
The problem you are mentioning here , there could be two ways to approach: 1. Check with your senior/manager who are more experienced than you whether they have faced similar issues , if so you will get the solution within your team or you may have a repository of Known Problem and Solution (KPS : such as bugzilla/jira/CRM) repostory within your company -- have a look there 2. You can open/raise a ticket. all EDA vendors have strong team of application engineers and they are very efficiently trained to solve customer issues. They are the right persons to help you with the tool specific query. Thanks for watching the video.
Sir I'm getting lwp failed with code[500]
Please follow these kind of RCA : th-cam.com/video/x6X8GyDoEUQ/w-d-xo.html
Very important video.... thank you for your hardwork
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amazing lecture, very insightful, It would have been a cherry on top if you would have given us an example by running the script code in the terminal itself, so that we could have got the idea if the output resembles with yours or not........
Here is the example : th-cam.com/video/DogAWB-Ym2s/w-d-xo.html
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Thanks you :) I have an ip exam tomorrow and this will hep
Hello my friends. I have encountered the following problem: There is a way to fix a Setup Violation called Register Duplication - by duplicating registers, the timing paths can be shortened, reducing the wire and cell propagation delays. This can be done in the following ways - Duplication can be done manually in the RTL or automatically by the synthesis and PnR tools. I have not found a way to do this in PnR tools (Innovus). Maybe you can tell me?
The problem you are mentioning here , there could be two ways to approach: 1. Check with your senior/manager who are more experienced than you whether they have faced similar issues , if so you will get the solution within your team 2. You can open/raise a ticket. all EDA vendors have strong team of application engineers and they are very efficiently trained to solve customer issues. They are the right persons to help you with the tool specific query. Thanks for watching the video.
hi sir can you make video on spice correlation in static timing analysis
explained here in detail : th-cam.com/video/kiGlPWOS-EI/w-d-xo.html
Really enjoyed the whole video and it's beneficial thanks for taking the initiative to make this video.
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Great video. Please could you provide the timestamps ?
Timestamps can be found in the video description
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@@TechSimplifiedTV I sure will. Your videos and channel are indeed a life saver. I’m currently studying for my masters degree in Microelectronics & Microsystems Engineering at German University. I’m familiar with many of these concepts as I have taken classes on them but your emphasis on practicals ( especially with open source software) and industry applications of these concepts makes all the difference.
This is really good. So I think one way of remembering the difference between lappend and concat: concat is all new and a little flat, lappend just adds to the end. Of all the list commands, only lset and lappend modify your list in place, the others all just return a value or create new lists as results. lset and lappend are just like set and append for lists.
There's even more that the -dictionary lsort option does for us. From the man pages: This is the same as -ascii except (a) case is ignored except as a tie-breaker and (b) if two strings contain embedded numbers, the numbers compare as integers, not characters. For example, in -dictionary mode, bigBoy sorts between bigbang and bigboy, and x10y sorts between x9y and x11y. Dang, that is pretty powerful to have at your fingertips at any and all times in your favorite scripting language.
This is a good video and I still like the series. Now, this is important to know though, the meaning and use of - as a body is not as you describe it. What happens when you put - as the body for a pattern means "use what you will use for the next pattern mentioned" which chains as far as it needs to until it finds a body that isn't - That is to say, your script you wrote will also call anything with 0 1 or 2 sides a triangle as well: % set no_of_edge 1 1 % switch $no_of_edge { 0 - 1 - 2 - 3 { puts "This is a triangle." } } This is a triangle. Still a worthwhile video, that distinction is important to switch behavior tho.
Hi, I believe the diode arrangements in the esd diagram is not correct. You may have placed them by mistake.
We will check !
keep uploading these videos <3 plz don't close you account even u get less followers increase, it's hard to find such videos related to vlsi
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very good work sir ,which helped me to learn many topics
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Very good video, thank you very much!
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