ALL ABOUT VLSI
ALL ABOUT VLSI
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"Deep Dive into UVM Sequence: Essential Methods, Body Task, and Driver Communication Explained!"
"In this video, we take a comprehensive look at the UVM Sequence in SystemVerilog, covering the fundamentals and advanced concepts that make sequences essential in UVM-based verification. You’ll learn about the body() task in detail, including key methods like start_item(), finish_item(), and randomize(), which enable smooth transaction flow between sequences and drivers. We also provide a practical code example showing how sequences generate transactions and how they communicate seamlessly with the driver. Whether you're new to UVM or looking to strengthen your verification skills, this video is for you! Don't forget to like, subscribe, and share for more in-depth UVM tutorials."
#UVMSequence
#SystemVerilog
#UVMTutorial
#SequenceMethods
#BodyTask
#VerificationEngineer
#SystemVerilogCoding
#TransactionLevelModeling
#Randomization
#TransactionFlow
#StartItem
#FinishItem
#VerificationSkills
#VLSITutorial
#HardwareVerification
#DigitalDesign
#LearnSystemVerilog
#UVMVerification
#SequenceItemPort
#SequenceItemExport
#SequencerToDriver
#FPGA
#ASICVerification
#UVMTestbench
#SequenceControl
#TransactionHandling
#CodingInSystemVerilog
#AdvancedVerification
#UVMBasics
#CodingTutorial
#VLSI
#UVMBestPractices
#DigitalLogicDesign
#HardwareDesign
#ElectronicsEngineer
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#EngineeringTips
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#ElectronicsTutorial
#EngineeringCommunity
#TestingAutomation
#SystemVerilogExperts
#FPGAProgramming
#CodingBasics
#VerificationMethodologies
#DesignAutomation
#HardwareSimulation
#UVMForBeginners
#HardwareDesignEngineer
#VLSITesting
#VerificationBasics
#DigitalVerification
#CircuitDesign
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#Microelectronics
#ASICDesign
#DigitalCircuits
#SystemDesign
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มุมมอง: 17

วีดีโอ

Problem solving session on Boolean Algebra || Digital Problem solving sessions30:58Problem solving session on Boolean Algebra || Digital Problem solving sessions
Problem solving session on Boolean Algebra || Digital Problem solving sessions
มุมมอง 6221 วันที่ผ่านมา
Problem solving session on Boolean Algebra || Digital Problem solving sessions
Introduction to UVM phases | UVM full course21:51Introduction to UVM phases | UVM full course
Introduction to UVM phases | UVM full course
มุมมอง 9321 วันที่ผ่านมา
Introduction to UVM phases | UVM full course
Introduction to Interface in System Verilog || part 1|| System Verilog full course ||17:25Introduction to Interface in System Verilog || part 1|| System Verilog full course ||
Introduction to Interface in System Verilog || part 1|| System Verilog full course ||
มุมมอง 9528 วันที่ผ่านมา
Introduction to Interface in System Verilog || part 1|| System Verilog full course ||
Factory overriding in UVM || UVM full course ||17:16Factory overriding in UVM || UVM full course ||
Factory overriding in UVM || UVM full course ||
มุมมอง 11328 วันที่ผ่านมา
Factory overriding in UVM || UVM full course ||
Passing arguments of tasks by value and pass by refernece || Tasks and functions part 2 ||20:50Passing arguments of tasks by value and pass by refernece || Tasks and functions part 2 ||
Passing arguments of tasks by value and pass by refernece || Tasks and functions part 2 ||
มุมมอง 5928 วันที่ผ่านมา
Passing arguments of tasks by value and pass by refernece || Tasks and functions part 2 ||
Tasks and Function in System verilog Part - 1|| System verilog full course ||24:17Tasks and Function in System verilog Part - 1|| System verilog full course ||
Tasks and Function in System verilog Part - 1|| System verilog full course ||
มุมมอง 79หลายเดือนก่อน
Tasks and Function in System verilog Part - 1|| System verilog full course ||
Introduction to UVM Factory - part 1 || UVM full course ||24:46Introduction to UVM Factory - part 1 || UVM full course ||
Introduction to UVM Factory - part 1 || UVM full course ||
มุมมอง 237หลายเดือนก่อน
Introduction to UVM Factory - part 1 || UVM full course ||
Write operation in I2C Protocol || I2C Protocol full course||20:29Write operation in I2C Protocol || I2C Protocol full course||
Write operation in I2C Protocol || I2C Protocol full course||
มุมมอง 88หลายเดือนก่อน
Write operation in I2C Protocol || I2C Protocol full course||
Introduction to Uvm test bench architecture part - 1 ||17:11Introduction to Uvm test bench architecture part - 1 ||
Introduction to Uvm test bench architecture part - 1 ||
มุมมอง 88หลายเดือนก่อน
Introduction to Uvm test bench architecture part - 1 ||
Understanding Queues in system verilog through coding || System verilog full course ||13:06Understanding Queues in system verilog through coding || System verilog full course ||
Understanding Queues in system verilog through coding || System verilog full course ||
มุมมอง 39หลายเดือนก่อน
Understanding Queues in system verilog through coding || System verilog full course ||
INTRODUCTON TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) || UVM FULL FREE COURSE ||11:53INTRODUCTON TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) || UVM FULL FREE COURSE ||
INTRODUCTON TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) || UVM FULL FREE COURSE ||
มุมมอง 472หลายเดือนก่อน
INTRODUCTON TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) || UVM FULL FREE COURSE ||
INTRODUCTION TO ARCHITECTURE OF I2C AND ESTABLISHING COMMUNICATION BETWEEN MASTER AND SLAVE || PART128:39INTRODUCTION TO ARCHITECTURE OF I2C AND ESTABLISHING COMMUNICATION BETWEEN MASTER AND SLAVE || PART1
INTRODUCTION TO ARCHITECTURE OF I2C AND ESTABLISHING COMMUNICATION BETWEEN MASTER AND SLAVE || PART1
มุมมอง 106หลายเดือนก่อน
INTRODUCTION TO ARCHITECTURE OF I2C AND ESTABLISHING COMMUNICATION BETWEEN MASTER AND SLAVE || PART1
Understanding Dynamic arrays through coding || System verilog full course ||22:56Understanding Dynamic arrays through coding || System verilog full course ||
Understanding Dynamic arrays through coding || System verilog full course ||
มุมมอง 49หลายเดือนก่อน
Understanding Dynamic arrays through coding || System verilog full course ||
Introduction to I2C protocol || I2C protocol full course ||21:52Introduction to I2C protocol || I2C protocol full course ||
Introduction to I2C protocol || I2C protocol full course ||
มุมมอง 274หลายเดือนก่อน
Introduction to I2C protocol || I2C protocol full course ||
Understanding packed arrays with coding || System verilog full course||17:35Understanding packed arrays with coding || System verilog full course||
Understanding packed arrays with coding || System verilog full course||
มุมมอง 36หลายเดือนก่อน
Understanding packed arrays with coding || System verilog full course||
Built in functions of Associative arrays in system verilog || System verilog full course ||17:01Built in functions of Associative arrays in system verilog || System verilog full course ||
Built in functions of Associative arrays in system verilog || System verilog full course ||
มุมมอง 46หลายเดือนก่อน
Built in functions of Associative arrays in system verilog || System verilog full course ||
Assosiative arrays in system verilog || System verilog full course ||25:36Assosiative arrays in system verilog || System verilog full course ||
Assosiative arrays in system verilog || System verilog full course ||
มุมมอง 51หลายเดือนก่อน
Assosiative arrays in system verilog || System verilog full course ||
Queues in system verilog || System verilog full course ||16:33Queues in system verilog || System verilog full course ||
Queues in system verilog || System verilog full course ||
มุมมอง 80หลายเดือนก่อน
Queues in system verilog || System verilog full course ||
Dynamic Arrays in System Verilog part 2 || System verilog full course ||18:30Dynamic Arrays in System Verilog part 2 || System verilog full course ||
Dynamic Arrays in System Verilog part 2 || System verilog full course ||
มุมมอง 52หลายเดือนก่อน
Dynamic Arrays in System Verilog part 2 || System verilog full course ||
Introduction to Dynamic arrays part - 1 || System verilog complete course ||20:46Introduction to Dynamic arrays part - 1 || System verilog complete course ||
Introduction to Dynamic arrays part - 1 || System verilog complete course ||
มุมมอง 102หลายเดือนก่อน
Introduction to Dynamic arrays part - 1 || System verilog complete course ||
Introduction to Fixed size arrays : Packed and Unpacked arrays || System verilog full course ||29:19Introduction to Fixed size arrays : Packed and Unpacked arrays || System verilog full course ||
Introduction to Fixed size arrays : Packed and Unpacked arrays || System verilog full course ||
มุมมอง 122หลายเดือนก่อน
Introduction to Fixed size arrays : Packed and Unpacked arrays || System verilog full course ||
Structures using typedef || Enum data types in system verilog || System verilog full course ||26:51Structures using typedef || Enum data types in system verilog || System verilog full course ||
Structures using typedef || Enum data types in system verilog || System verilog full course ||
มุมมอง 162หลายเดือนก่อน
Structures using typedef || Enum data types in system verilog || System verilog full course ||
Introduction to structures in system verilog part - 1 || System verilog full course ||19:07Introduction to structures in system verilog part - 1 || System verilog full course ||
Introduction to structures in system verilog part - 1 || System verilog full course ||
มุมมอง 206หลายเดือนก่อน
Introduction to structures in system verilog part - 1 || System verilog full course ||
Introduction to Logic data type and 2 state data types || Data types in system verilog ||18:20Introduction to Logic data type and 2 state data types || Data types in system verilog ||
Introduction to Logic data type and 2 state data types || Data types in system verilog ||
มุมมอง 185หลายเดือนก่อน
Introduction to Logic data type and 2 state data types || Data types in system verilog ||
Calculation of setup and hold time by considering negative skew || Static timing full course ||14:31Calculation of setup and hold time by considering negative skew || Static timing full course ||
Calculation of setup and hold time by considering negative skew || Static timing full course ||
มุมมอง 41หลายเดือนก่อน
Calculation of setup and hold time by considering negative skew || Static timing full course ||
Introduction to System Verilog || System verilog full course Batch - 2 ||11:12Introduction to System Verilog || System verilog full course Batch - 2 ||
Introduction to System Verilog || System verilog full course Batch - 2 ||
มุมมอง 390หลายเดือนก่อน
Introduction to System Verilog || System verilog full course Batch - 2 ||
Frequently asked questions in number systems || Digital mock interview part 1 ||28:03Frequently asked questions in number systems || Digital mock interview part 1 ||
Frequently asked questions in number systems || Digital mock interview part 1 ||
มุมมอง 85หลายเดือนก่อน
Frequently asked questions in number systems || Digital mock interview part 1 ||
Timing equations for Setup and Hold time with positive skew in clock || Sta full course ||21:53Timing equations for Setup and Hold time with positive skew in clock || Sta full course ||
Timing equations for Setup and Hold time with positive skew in clock || Sta full course ||
มุมมอง 69หลายเดือนก่อน
Timing equations for Setup and Hold time with positive skew in clock || Sta full course ||
Derivation of setup and hold time equations without considering Clock skew || Day 8 Sta full course20:43Derivation of setup and hold time equations without considering Clock skew || Day 8 Sta full course
Derivation of setup and hold time equations without considering Clock skew || Day 8 Sta full course
มุมมอง 63หลายเดือนก่อน
Derivation of setup and hold time equations without considering Clock skew || Day 8 Sta full course

ความคิดเห็น

  • @ramudukuruva3145
    @ramudukuruva3145 13 ชั่วโมงที่ผ่านมา

    Nice explanation

  • @hamza001_9
    @hamza001_9 วันที่ผ่านมา

    When will the next i2c video be uploaded? For the final complete module and the testbench?

  • @pathakamurinaresh8041
    @pathakamurinaresh8041 2 วันที่ผ่านมา

    🎉🎉

  • @pathakamurinaresh8041
    @pathakamurinaresh8041 2 วันที่ผ่านมา

    🎉🎉

  • @fabiyaca
    @fabiyaca 6 วันที่ผ่านมา

    I paid for the course. Please provide it.

    • @Allaboutvlsii
      @Allaboutvlsii 6 วันที่ผ่านมา

      hi @fabiyaca please check your mail we have refunded your amount and attached screenshot of payment since the course has completed. please wait for next batch registration

  • @ramudukuruva3145
    @ramudukuruva3145 6 วันที่ผ่านมา

    Super

  • @ngocmanprocoder
    @ngocmanprocoder 8 วันที่ผ่านมา

    Hi, could you send me questaSim installation files, please? Many thanks.

  • @ManojDas-uf1zk
    @ManojDas-uf1zk 10 วันที่ผ่านมา

    Is it full axi protocol or something else to learn please tell me I am staring axi protocol

  • @Allaboutvlsii
    @Allaboutvlsii 11 วันที่ผ่านมา

    note the mistake in the answer , the last question answer is 564

  • @nithishkanna7
    @nithishkanna7 12 วันที่ผ่านมา

    at 8:37 how does rs1 stores 32 bits since the overall size of the i type register is 32 bit

    • @Allaboutvlsii
      @Allaboutvlsii 12 วันที่ผ่านมา

      here the data is present in the instruction that is 12 bits and it is to be stored inside the rs1 register which of 32 bits therefore the data is sign extended before we store it into the rs1 register hope you understood

    • @nithishkanna7
      @nithishkanna7 12 วันที่ผ่านมา

      @@Allaboutvlsii but you mentioned the size of rs1 register is 5 bits but when you write you mentioned the size of rs1 register alone 32 bits, sir

    • @Allaboutvlsii
      @Allaboutvlsii 12 วันที่ผ่านมา

      @@nithishkanna7 here rs1 refers to source register address which is of 5 bits . i.e it is telling us where to take the second operand and first operand is immediate value. and this immediate value is sign extended to 32 bits, the second operand is stored in one of the 32 32 bit registers that address is given by rs2 register. and finally the result is stored in one of the 32 registers whose address is given in rd

    • @nithishkanna7
      @nithishkanna7 12 วันที่ผ่านมา

      @@Allaboutvlsii does that mean the 5 bits you mentioned in rs1 represents address but it can hold 32 bit data for that address, am i right, sir?

    • @Allaboutvlsii
      @Allaboutvlsii 12 วันที่ผ่านมา

      @@nithishkanna7 it is address for 32 bit register that can hold the data

  • @Allaboutvlsii
    @Allaboutvlsii 14 วันที่ผ่านมา

    hey all, in the formulae which we have discussed in the session for diminished radix complement, the variable n stands for number of digits which i tried explain in the video but i think it will not clearly audible due to network issue, i will try to explain the same in next session

  • @gayathrigarlapati215
    @gayathrigarlapati215 14 วันที่ผ่านมา

    Sir, Is this Playlist of 20 videos is full course or is there more videos also?

    • @Allaboutvlsii
      @Allaboutvlsii 14 วันที่ผ่านมา

      no still we have so many topics , classes will resume from today live at 8 pm

  • @Allaboutvlsii
    @Allaboutvlsii 18 วันที่ผ่านมา

    Hey everyone small modification in the test bench code, i have used same initial begin block for clock generation and stimulus driving because of that the code was running forever. Instead of that use two blocks.

  • @nithishkanna7
    @nithishkanna7 19 วันที่ผ่านมา

    Does wvalid signal sets to high before awready signal sets to high? If it is yes and can you please expalin why? If wvalid sets to high before awready signal, doesn't mean the master is about to transmit write data before transmitting write address.

    • @Allaboutvlsii
      @Allaboutvlsii 19 วันที่ผ่านมา

      awready signal is asserted by the slave that it is ready to accept the data. wvalid signal should wait for the address phase to get completed that is after asserting awready signal by the slave then only the wvalid signal is asserted by the master indicating the write phase. yes if wvalid sets to high before awready signal that means without completing the address phase itself we are going to start the write phase

    • @nithishkanna7
      @nithishkanna7 19 วันที่ผ่านมา

      @@Allaboutvlsii thanks for your response

  • @cyanical_storm908
    @cyanical_storm908 20 วันที่ผ่านมา

    sir please upload the i2c programming video

    • @Allaboutvlsii
      @Allaboutvlsii 20 วันที่ผ่านมา

      Yes sure it will be uploaded in next week

  • @MSQ819
    @MSQ819 22 วันที่ผ่านมา

    you need to work on your explaining skill

  • @swetha.pgowda6234
    @swetha.pgowda6234 26 วันที่ผ่านมา

    Hi, what is the software you used to write this code?

  • @channameshsangannavar4523
    @channameshsangannavar4523 27 วันที่ผ่านมา

    Nice explanation

  • @PragatiPiragannavar
    @PragatiPiragannavar 27 วันที่ผ่านมา

    tqu...sir

  • @ashutoshece651
    @ashutoshece651 28 วันที่ผ่านมา

    Buils phase follow top to down approach...#correction

    • @Allaboutvlsii
      @Allaboutvlsii 28 วันที่ผ่านมา

      yeah its top to down

  • @nithishkanna7
    @nithishkanna7 29 วันที่ผ่านมา

    sir can you explain this doubt please? when we are s2 then how are going to s3 since you mentioned if enable==1 -> next state=s1 and enable=0->next state =idle;

    • @Allaboutvlsii
      @Allaboutvlsii 25 วันที่ผ่านมา

      i didnt get your question where we are going to s3 from s2?

  • @nithishkanna7
    @nithishkanna7 29 วันที่ผ่านมา

    sir at line 34, why did you mention clk within the brackets and also you mentioned clk instead of hclk, because you declared hclk as input

    • @Allaboutvlsii
      @Allaboutvlsii 25 วันที่ผ่านมา

      hi nithish thanks for pointing out its a mistake from my side

  • @gokulp6878
    @gokulp6878 หลายเดือนก่อน

    can you please explain ral?

  • @nithishkanna7
    @nithishkanna7 หลายเดือนก่อน

    what do you mean by address boundary, how did you define it and why it wraps around address boundary in wrapping burst and not happening in incremental burst? can u plz explain sir

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      an address boundary is like a maximum address limit. In case of incremental burst, burst address can exceed this limit, but in case of wrapping burst as the name suggests it will wrap around to the initial address if it reaches a specific address.

    • @nithishkanna7
      @nithishkanna7 หลายเดือนก่อน

      @@Allaboutvlsii thank you so much sir

  • @SureshYadav-xb7zh
    @SureshYadav-xb7zh หลายเดือนก่อน

    Can you send pdf of this

  • @yashrajlatta5104
    @yashrajlatta5104 หลายเดือนก่อน

    can you suggest some books to read from?

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      you can refer the official risc v documentation available online

  • @KushagraShukla-jb5cr
    @KushagraShukla-jb5cr หลายเดือนก่อน

    please dont stop uploading these videos, you teach so good......also will you cover the design, verification, UVM, assertions and oops concepts here??

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      Thank you.. Yes entire sv will be covered

  • @kavitagaur9829
    @kavitagaur9829 หลายเดือนก่อน

    when input is 1 at case how we avoid OR gate because in second mux it pointed out at 0

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      hi @kavitagaur9829, can you please reframe your question i'm not getting it

  • @navneetdubey8176
    @navneetdubey8176 หลายเดือนก่อน

    Sir waiting for next topic(video lecture)

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      Hi navneet this is the last topic in the playlist

  • @abhishekananda5317
    @abhishekananda5317 หลายเดือนก่อน

    bhai itna rat ke kon bolta hai yaar??

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      I accept that those where my initial days of teaching

  • @AshokNaik_20
    @AshokNaik_20 หลายเดือนก่อน

    Uvm please

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      Starting from 31 sept

  • @GoldenDucky1
    @GoldenDucky1 หลายเดือนก่อน

    I expect that you will do pipeline for this cpu

  • @manjunadha4636
    @manjunadha4636 หลายเดือนก่อน

    please share notes

  • @AshokNaik_20
    @AshokNaik_20 หลายเดือนก่อน

    Uvm please bro!

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      Definetly i will launch pls wait

  • @MrVybhava
    @MrVybhava หลายเดือนก่อน

    Excellent work

  • @sharanyatammara1791
    @sharanyatammara1791 หลายเดือนก่อน

    very helpful

  • @sharanyatammara1791
    @sharanyatammara1791 หลายเดือนก่อน

    yayyy

  • @sharanyatammara1791
    @sharanyatammara1791 หลายเดือนก่อน

    lesgoooo

  • @sharanyatammara1791
    @sharanyatammara1791 หลายเดือนก่อน

    moss

  • @arpan1930
    @arpan1930 หลายเดือนก่อน

    how can i join this risc-v course?

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      hi arpan we have completed the course you can watch the recording and if having any doubts you can comment here

  • @AshokNaik_20
    @AshokNaik_20 หลายเดือนก่อน

    Bro when u start UVM?

  • @GoldenDucky1
    @GoldenDucky1 หลายเดือนก่อน

    LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros or I mistake this.

    • @Allaboutvlsii
      @Allaboutvlsii หลายเดือนก่อน

      Yes you are correct there is a mistake i have done here

  • @maharshitrivedi9545
    @maharshitrivedi9545 2 หลายเดือนก่อน

    1:36 write response slave-> master

  • @GoldenDucky1
    @GoldenDucky1 2 หลายเดือนก่อน

    Can you share source code

    • @Allaboutvlsii
      @Allaboutvlsii 2 หลายเดือนก่อน

      github.com/GOURAV-CTRL/RISC-V

    • @GoldenDucky1
      @GoldenDucky1 2 หลายเดือนก่อน

      @@Allaboutvlsii Thanks

    • @GoldenDucky1
      @GoldenDucky1 2 หลายเดือนก่อน

      @@Allaboutvlsii Can you add file register_file

  • @thegreat5539
    @thegreat5539 2 หลายเดือนก่อน

    Notes please

  • @thegreat5539
    @thegreat5539 2 หลายเดือนก่อน

    Notes please

  • @nirbhaythakkar9931
    @nirbhaythakkar9931 2 หลายเดือนก่อน

    how much more videos sir? and will we cover sv tb ?

    • @Allaboutvlsii
      @Allaboutvlsii 2 หลายเดือนก่อน

      I think 5 to 6 more and will see wheather to cover sv

  • @jojwilliam4174
    @jojwilliam4174 2 หลายเดือนก่อน

    Wait is finally over thankyou so much

  • @lucky-qz7vx
    @lucky-qz7vx 2 หลายเดือนก่อน

    sir please do more videos

  • @allenhr325
    @allenhr325 2 หลายเดือนก่อน

    Thank you for sharing this ...