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John Reuben
เข้าร่วมเมื่อ 26 พ.ย. 2014
Resistive RAM (memristor) Modeling and In-memory Computing using Majority Logic
This is a guest lecture in which I summarize my recent work on ReRAM modeling and in-memory computing. In the first part of the talk (~ 25 mins) I talk about ReRAM modeling -how to take the Stanford-PKU model and fit it to any ReRAM device. In the second half of the talk, I discuss how a majority gate can be implemented in a ReRAM array with minimal change to the peripheral circuitry. Computing is simplified to a sequence of memory READ and WRITE operations. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is
demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. A 32-bit adder can be implemented in 26 cycles, which is one of the fastest in-memory adders reported so far.
For more details, see:
1. John Reuben and Stefan Pechmann, "Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2021.3068470.
2. John Reuben, Mehrdad Biglari and Dietmar Fey, "Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford-PKU Model," in IEEE Transactions on Nanotechnology, vol. 19, pp. 508-518, 2020, doi: 10.1109/TNANO.2020.3004666.
3. John Reuben, Dietmar Fey and Christian Wenger, "A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability," in IEEE Transactions on Nanotechnology, vol. 18, pp. 647-656, 2019, doi: 10.1109/TNANO.2019.2922838.
demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. A 32-bit adder can be implemented in 26 cycles, which is one of the fastest in-memory adders reported so far.
For more details, see:
1. John Reuben and Stefan Pechmann, "Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2021.3068470.
2. John Reuben, Mehrdad Biglari and Dietmar Fey, "Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford-PKU Model," in IEEE Transactions on Nanotechnology, vol. 19, pp. 508-518, 2020, doi: 10.1109/TNANO.2020.3004666.
3. John Reuben, Dietmar Fey and Christian Wenger, "A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability," in IEEE Transactions on Nanotechnology, vol. 18, pp. 647-656, 2019, doi: 10.1109/TNANO.2019.2922838.
มุมมอง: 7 144
วีดีโอ
Mesh based clock distribution
มุมมอง 4.3K8 ปีที่แล้ว
In this lecture, i discuss mesh-based clock distribution method which has received much attention since 2010. Clock mesh is more resistant to on-chip variations when compared to tree, but this achieved at cost of more power.
Left Edge and Dogleg Algorithm for channel routing
มุมมอง 21K8 ปีที่แล้ว
In this lecture, the left edge algorithm for Channel routing in VLSI physical design is discussed with an example. This basic algorithm is crucial for all advances in channel routing. The dogleg algorithm, which improves the left edge algorithm by net-splitting is also discussed.
Sequence Pair for VLSI Placement
มุมมอง 9K8 ปีที่แล้ว
The Sequence pair is a concise representation of non-slicing floor plan. In this lecture, i introduce sequence pair representation and illustrate how it can be used together with simulated annealing for optimization in VLSI placement. I also discuss an example from the book "Practical problems in VLSI PDA" by Sung Kyu Lim
Floor Planning by Integer Linear Programming(ILP)
มุมมอง 8K8 ปีที่แล้ว
Integer Linear Programming(ILP) is a general optimization technique. In this algorithm the floor planning problem in VLSI physical design is formulated as an ILP and solved.
Layout of Inverter, Cadence Virtuoso,90 nm: Part-2
มุมมอง 14K9 ปีที่แล้ว
In this lab demo, we show how to do post layout simulation of a CMOS inverter using Cadence Virtuoso, Technology-90 nm
Layout of Inverter in Cadence Virtuoso,90 nm-Part1
มุมมอง 45K9 ปีที่แล้ว
In this lab demo, we show how to draw the layout of a CMOS inverter using Cadence Virtuoso, Technology-90 nm.
Kernighan-Lin(KL) algorithm for Partitioning
มุมมอง 52K9 ปีที่แล้ว
KL algorithm is an iterative improvement algorithm for bi-partitioning a netlist.Belonging to the class of group migration algorithms, it is based on exchanging a pair of nodes across the partition to reduce the cutset.In this lecture, the algorithm is explained with an example.
Partitioning-an Introduction
มุมมอง 7K9 ปีที่แล้ว
In this lecture, i give an introduction to Partitioning, which is the first step in VLSI physical design automation.
Floor Planning by Polish Expression continued
มุมมอง 4.2K9 ปีที่แล้ว
The continuation of my previous lecture on floor planning using polish expression. The 3 moves suggested by Wong and Liu are illustrated.
Floor planning by Polish Expression
มุมมอง 14K9 ปีที่แล้ว
The polish expression, proposed by Wong and Liu is a succinct representation of slicing floor plans. In this lecture, I explain how floor plans can be represented by polish expressions and how simulated annealing can be used to optimize the floor plan.
Introduction to Floor planning
มุมมอง 23K9 ปีที่แล้ว
In this lecture, I give an introduction to floor planning -the phase in physical design flow after partitioning where the modules are assigned a tentative location on the chip. The goal of floor planning algorithm is to determine optimum locations for the blocks such that the interconnections between them are routable. Includes an interesting animation on slicing tree to represent a floorplan
LCM based Clock Generation
มุมมอง 3189 ปีที่แล้ว
This audio slide is a short presentation of my research “A Novel Clock Generation Algorithm for System-on-Chip based on Least Common Multiple ” published by Computers and Electrical Engineering, ELSEVIER, Vol.40, Issue 7, 2014
Exact Zero Skew Algorithm
มุมมอง 3.7K9 ปีที่แล้ว
The exact zero skew clock routing algorithm, proposed by Tsay in 1993 is still used in many clock tree synthesis tools. This algorithm is foundational to all the latest developments in clock distribution. this lecture presents the algorithm with an example
Clock distribution network
มุมมอง 8K9 ปีที่แล้ว
In this lecture, i give an introduction to one of the crucial aspects of physical design- the clock distribution network.
Sir, can you provide that ppt ?
Good explanation and in-depth information. Thank you for the video!
great lecture!
Thank you so much 👏👏👏
great tutorial
Perfect!!!
Very good video! Greetings from Italy.
Impressive, Thank you so much !
🙏🙏Thank you sir
Thanks bro
good
Awesome!
very nice explanation sir
TQSM it was very helpful
Sir, please check with A to C in graph
Thank you sir!
I clicked the option in boundary only while starting layout
Sir that active area boundary automatically disappears sir. What to do?
Thank you sir
Well explained thank you
i got errors NIMP.A.1: Nimp area must be >=0.15 um PIMP.A.1: Pimp area must be >=0.15 um what does they mean sir
The are of the Pimplant and Nimplant must be greater than the or equal to that values For example, I am going to take the values that you have taken. The height of the cell is 0.7μm and the length of that implant is considered as 0.3μm then the are going to become 0.21μm it means here your error is clear. These specifications are going to be generated by the Fabracitaion team hence these values are not fixed for the same technology also it will be dependent on the company of fabrication.
Sir i need c program to perform the left edge algorithm
good evening...
good evening sir...thank you... you helped me for my test
Respected Sir I am a 4th yr ECE Student. I am familiar with the Layout designing of basic gates in Cadence Virtuoso using 90nm and 180 nm tech nodes with DRC and LVS. I am looking for guidance from an experienced person related to this field. Thank You
hi... I have some question regarding 90nm cmos process..Can you help me out
Due to COVID19 Pandemic colleges are not opening and I can't access the cadence software so I searched for an open source software and I found GLADE. Check out my playlist on Layout Designing using GLADE. #LearnFromHome Playlist Link:- th-cam.com/play/PLWcG9vtrFH0YVZvd3yf2Xmm_Gl0y-XXz6.html Video 2&3: Glade Downloading, Setup and Configuration. Video 2 link: th-cam.com/video/LMZ3O6Akfro/w-d-xo.html Video 3 link: th-cam.com/video/1ueSinMmqkA/w-d-xo.html Video 4: Designing Layout of nMOS and pMOS is explained. Video 4 link: th-cam.com/video/oOblwp65WFA/w-d-xo.html Video 5: Designing CMOS Inverter Layout using 1 metal layer is explained in detail. Video 5 link: th-cam.com/video/Qr0nTPo-Ri0/w-d-xo.html Video 6: Verification of Designed Inverter Layout using LT Spice. Video 6 link: th-cam.com/video/kvrF6Zv6Y_U/w-d-xo.html Video 7: Designing CMOS Inverter Layout by using 2 metal layers and Vias. Video 7 link: th-cam.com/video/HZopqROB2GA/w-d-xo.html Video 8: Designing 2 Input CMOS NAND Gate. Video 8 link: th-cam.com/video/41067AYX_do/w-d-xo.html Video 9: Verification of Designed NAND Gate Layout using LT Spice. Video 9 link: th-cam.com/video/3pufZ6InuHQ/w-d-xo.html Video 10: Designing 2 Input CMOS NOR Gate. Video 10 link: th-cam.com/video/skYC2UnJgQ4/w-d-xo.html Kindly Like, Share among your engineering friends so that they can also learn from home and subscribe to my Channel for more GLADE Tutorials. Your Support will be appreciated. Thank You
Thanks for the awesome video, simulated annealing video is missing.Can you please upload it
Thank you, great explanation!!
NICE REUBEN
Sir I m new to this cadence do I get cadence for windows OS and can I get a trial version
And when I try to flatten the selected instance even though I hv given to preserve pins I get lavs error saying nmos on schematic is inbound to any layout device
Please do help me to clear this
Crystal clear ,Thanks for this video sir
A very well explained video for this topic. I learned a lot from you. Thank you, sir, you are great. Please, upload more videos.
can i have u r mail id plz sir
Wow! This is the best explanation of KL Algorithm on TH-cam. Thank you, brother. It was very helpful.
I am glad it helped you!
Sir can you make the videos for FM algorithm and simulated annealing algorithm.
Example starts at minute 23.
Thank you
Hi Ashish, Sorry, i am not aware of any documentation on the exact width of power/mesh ring.
i have not coded it. You can use a high-level language (like C or MATLAB) and code the steps of KL algorithm
Thank you sir
Would it be possible to share the c code behind turning a sequence pair into a HCG and VCG?
Sir told me zener diode parameters in analoglib cadence tool
I just didn't understand one thing: does the M3 perturbation in SA approach change the sequence pair as M1 and M3 do?
Excellent work Sir, Thank You so much. It was a great help to me.
Simply amazing!! You made it look so easy.
Very clear. Now I can do my homework!
Very helpful, Please come up with more examples and explanations with different analog layout concepts.
I read the reference book and I have a question: How can I calculate the coordinates of blocks without the tree? Actually, how can I calculate with just this representation: 25V1H374VH6V8VH
Since it was 4 years ago you wrote the comment, but write it because maybe some others that doesn't know also can read. You need to know about postfix and prefix. This is how we read tree as sentence representation, and the representation is fixed per each tree. It means you can convert the representation to tree.
Thanks for this video I have a question: How we obtain the location of blocks in the x-y axis? actually how we convert the polish representation to x-y representation?
I think you are wrong about the Left edge algo. You have to iterate through the whole order before starting from the left again, according to the algorithm provided in these slides.
Yes