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Its not working. Now its showing file cant be locked, so read only option is available

Sir can you share power dissipation calculation for transmission gate,for transmission gate for ac analysis i was getting stright line at 0w,can you please help me

Bundle of Thanks dear Waqar bhatt for making such a great tutorials, enjoying your video series. ❤

You are an outstanding teacher.

Bro, how to find/estimate threshold voltage of gpdk45nm Nmos or Pmos transistor in cadence. could you Please explain?

Thank you, this solution works if we r not able to enter into the editor window, I am facing an issue that even after entering the editable window I am not able to edit the design, can plz reply what procedure to follow

Hello sir, Slew rate for two stage opamp is Iss/Cc na You have taken Iss/CL....

MOSFET below the diff pair is in linear region, how to fix it?

Which one is more accurate value of gm , the one we get by calculating on calculator or the one in annotations ( dummy analysis) ?

how do you know to measure the transconductance at the voltage point you set vgs to be ? Why didnt you look at the point at which the derivative graph peaks as that would give the maximum transconductance?

Very nice explanation❤

Best one

You are such a great instructor man.

If you video was in English you will get a lot of views. Plus the videos that are watched by the people from western countries you get paid more because of the western commercials. You tube will pay you more if more people from western countries are watching your videos.

Thank you

What Basically Fingers meant For?

Sir how to calculate noise margin if we have multiple number of inputs?

Any idea how to plot transconductance vs Vgs ?

from where to install that library

Thank you Sir❤️💯 Helped mea lot for my Analog IC Design Assignment...Keep it up👍🏻

tomorrow is my exam thanks for the lecture

Watch This today and i really love it❤

Waqas bhai, cādence software koi jageh sey free mey install kr saktey h?

Hi Thank you for making this video, I was wondering how you came up with Vg = Vs + Vth + 5% of Vdd? Is it because we set the Vout = 0.5*VDD? Thank you.

Too Helpful... Was stuck at this, now got solved....Make more videos related to virtuoso...

can you upload video on how to install virtuoso cadence in windows??

Please upload more videos regarding analog IC design

Hi, sir your video is awesome and your explanation is easy to understand analog IC design I also looking for more videos about analog IC design

bro , how to install assura in the cracked version . please bro make a video or help me

Nice

Bro can you provide the Cadence link to download please respond

Thank you so much for this

Sir , please make video on installation process Virtuoso Cadence latest available Nhi hai , please request 🙏🙏

What happens if I calculate the delay without cap

Good content on your channel sir. Please create a SRAM cell simulation video as soon as possible.

Hello sir I got good understanding about BGR.. One question I have to ask will I replace BJT with p or n type MOSFET?? If yes then what will be the size??

great tutorial 😀

Hey i did not get the results with same values you used, it seems you are showing fake results

How to fix this --> Direcy Plot Form [Subwindow] ERROR: Total power is not a saved output

How to download cadence tool.tell me in comments

How can I install gpdk180? I am a college student so could you share this for academic propose?

Can you please share all your PDF handouts on Google Drive thanks

Sadly I don't understand the language here :(

thank you thank you thank youu

Sir can u show how Monte Carlo simulation steps

How gain can be achieved

Can you post how to get the 32nm library files and it is used in cadence virtuoso

Thanks a lot man! Keep Going!

Sir, can u show how to use the pass transistor for AND logic

can you share document that you shown in the video